System for designing re-programmable digital hardware platforms

Abstract

A digital design system and method are provided for re-programmable hardware platforms, such as field programmable gate arrays (FPGAs) and other re-programmable system designs. The design system and method bridge the gap between what has previously been a development and prototyping platform used during the design phase of an electronic design system (EDS) project, and commercially viable re-programmable product platforms to replace non-programmable platforms, such as discrete processors and ASICs.

1 . A method for digital circuit design, comprising the steps of:
 placing and wiring schematic components directly within a design capture environment familiar to users to enable them to build a design without the common requirement for advanced HDL knowledge and expertise;   instantiating the components into a design by the user; and   targeting the design to a re-programmable device;   thereby enabling the user to design by placing generic schematic symbols to produce a design.   
   
   
       2 . The method of  claim 1 , further comprising the step of:
 providing pre-synthesized components as object code entities without having to expose the underlying RTL-level source code.   
   
   
       3 . The method of  claim 1 , further comprising the step of:
 providing multiple libraries comprising a comprehensive set of pre-synthesized components, ranging from simple gate-level functional blocks, up through high-level hardware, and high-level functions.   
   
   
       4 . The method of  claim 1 , further comprising the steps of:
 providing models for generic, vendor-independent components; and   storing the models in a hierarchy of folders according to vendor and device family.   
   
   
       5 . The method of  claim 4 , further comprising for the step of:
 enabling a target re-programmable device to be changed at any time during in the design; and   re-linking all of the generic component symbols to the relevant pre-synthesized EDIF models for the device, found within the folders;   thereby enabling vendor independency.   
   
   
       6 . The method of  claim 4 , further comprising the steps of:
 providing user-created pre-synthesized EDIF models; and   storing the user-created models in one of a single user model folder or in a hierarchy of folders if the user is developing a model for multiple target devices.   
   
   
       7 . The method of  claim 1 , further comprising the step of:
 automatically re-targeting a generic design for a selected re-programmable device.   
   
   
       8 . The method of  claim 1 , wherein the re-programmable device is an FPGA, further comprising the steps of:
 using a single Process Flow when processing a captured FPGA design, the Process Flow consisting of four stages: 1) Compile, 2) Synthesize, 3) Build, and 4) Program FPGA.   
   
   
       9 . The method of  claim 1 , further comprising the step of:
 automatically managing device-specific design constraints associated with implementation data.   
   
   
       10 . The method of  claim 9 , further comprising the step of:
 storing the implementation data separate from source design documents;   thereby easily re-targeting the same design to a different physical FPGA device, allowing design portability.   
   
   
       11 . The method of  claim 1 , further comprising the step of:
 providing a development platform for interactive, re-targetable hardware/software co-design of a re-programmable device;   thereby allowing a single development platform to provide development resources for an unlimited number of target devices from one or more different semiconductor manufacturers.   
   
   
       12 . The method of  claim 11  wherein the development platform comprises a standard socket for installing various daughter boards, each of which houses a physical device that is to be used for development. 
   
   
       13 . The method of  claim 12  wherein each daughter board generates an identification code that is read by a controller, which can then program the physical device at power-up. 
   
   
       14 . The method of  claim 11 , further comprising the steps of:
 interconnecting a plurality of development platforms; and   employing a single pin on a header to detect and allow another development platform with JTAG devices to be automatically brought into a main JTAG chain.   
   
   
       15 . The method of  claim 1 , further comprising the step of:
 providing a generic boot system capable of supporting multiple re-programmable device architectures.   
   
   
       16 . The method of  claim 15  wherein the generic boot system provides support to program, at power-up, multiple re-programmable device architectures from different vendors. 
   
   
       17 . The method of  claim 15  wherein the boot system comprises a controller and a generic low-cost serial flash RAM device, and further comprising the step of storing in the flash RAM configuration data, wherein a type of re-programmable device from multiple vendors installed on a daughter board is read via an identification code from the daughter board and based on the identification, the configuration data from the flash RAM is used to select a correct programming algorithm to program the re-programmable device. 
   
   
       18 . The method of  claim 14 , further comprising the step of providing a single set of wires to handle multiple multiplexed JTAG and SPI communication channels. 
   
   
       19 . The method of  claim 11 , further comprising the step of controlling a clock frequency using of the re-programmable device using host-based development software. 
   
   
       20 . The method of  claim 12 , further comprising the step of providing a programmable power supply on the development platform for accommodating daughter boards with different power rail requirements.