Block addressing for parallel memory arrays

Abstract

Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache.

1 . An apparatus for organizing access for matched blocks of data spread among two or more disparate memory arrays, the apparatus comprising:
 an address translator configured to receive at least a block portion of logical addresses originating from a processor, wherein the block portion corresponds to an address range for selecting blocks of memory, wherein the address translator is configured to modify at least the received block portion of the received logical addresses to generate at least one of first modified addresses or second modified addresses, wherein the first modified addresses are for selection of memory blocks for a first memory array of the two or more memory arrays, wherein the second modified addresses are for selection of memory blocks for a second memory array of the two or more memory arrays, wherein the first modified addresses and the second modified addresses are configured to select matched blocks of the first memory array and the second memory array, respectively, using a same logical address for a block portion of the logical address;   a first row decoder in communication with the address translator to receive the first modified addresses, the first row decoder coupled to the first memory array; and   a second row decoder in communication with the address translator to receive the second modified address, the second row coupled to the second memory array, the second row decoder independent of the first row decoder.   
   
   
       2 . The apparatus of  claim 1 , wherein the address translator comprises at least one lookup table. 
   
   
       3 . The apparatus of  claim 1 , wherein the address translator, the first row decoder, the second row decoder, the first memory array, and the second memory array are embodied in an integrated circuit. 
   
   
       4 . The apparatus of  claim 1 , wherein the address translator is further configured to translate the received logical addresses to modified addresses for each of the two or more memory arrays. 
   
   
       5 . The apparatus of  claim 1 , further comprising two or more memory arrays of NAND flash for the two or more memory arrays. 
   
   
       6 . The apparatus of  claim 1 , wherein the address translator is programmable. 
   
   
       7 . The apparatus of  claim 1 , wherein at least a portion of the address translator is embodied as a programmable row decoder for the first memory array or the second memory array. 
   
   
       8 . The apparatus of  claim 1 , wherein the apparatus is embodied in a controller outside of a memory device. 
   
   
       9 . The apparatus of  claim 1 , wherein the apparatus is embodied within a memory device. 
   
   
       10 . A method of matching blocks of memory space for two or more memory arrays for access of data associated with the matching blocks using a same logical address, the method comprising:
 associating usable good blocks of a first array of the two or more memory arrays with usable good blocks of a second array of the two or more memory arrays in a contiguous logical address space such that matching good blocks of memory for the two or more memory arrays are logically addressable with a same logical address for a block portion of the logical address, wherein at least a portion of the usable good blocks of the first array associated with the good blocks of the second array have different physical addresses, and wherein the associated good blocks of the first array and the second array are accessible at the same time even with disparate physical addresses; and   storing the associations for logical address translation.   
   
   
       11 . The method of  claim 10 , wherein storing further comprises programming one or more lookup tables to store associations of good blocks from the two or more memory arrays and logical addresses. 
   
   
       12 . The method of  claim 11 , further comprising storing parameters that substitute for a block portion of logical addresses to store the associations. 
   
   
       13 . The method of  claim 11 , further comprising storing offsets that combine with logical addresses to store the associations. 
   
   
       14 . The method of  claim 10 , further comprising storing the associations via programming of one or more row decoders. 
   
   
       15 . The method of  claim 10 , wherein associating comprises:
 determining whether blocks of a memory array are good or bad;   sequentially associating addresses starting from a beginning address for the memory array for the good blocks of the memory array in a contiguous address space; and   associating the bad blocks of the memory array with addresses at an end of an address range for the memory array.   
   
   
       16 . The method of  claim 10 , further comprising performing the method during production test. 
   
   
       17 . The method of  claim 10 , further comprising performing the method in a field application. 
   
   
       18 . A method of modifying addresses for access to two or more disparate memory arrays, the method comprising:
 receiving logical addresses from a processor for access to memory locations of two or more disparate memory arrays, wherein block portions of the logical addresses relate to addressing of particular blocks within memory arrays;   generating first modified addresses for a first memory array from the logical addresses and stored parameters corresponding to selected memory blocks of the first memory array to rearrange access to the selected memory blocks such that at least a first group of good memory blocks of at least a minimum number of good memory blocks specified for the first memory array is accessible in a contiguous logical memory address space and such that bad blocks are not addressed within the contiguous logical memory address space;   generating second modified addresses for a second memory array from the logical addresses and stored parameters corresponding to selected memory blocks of the second memory array to rearrange access to the selected memory blocks such that at least a second group of good memory blocks of at least a minimum number of good memory blocks specified for the second memory array are accessible in the contiguous logical memory address space and such that bad blocks are not addressed within the contiguous logical memory address space; and   using the first modified addresses and the second modified addresses to access matched blocks of the first memory array and the second memory array such that the matched blocks are addressable by the processor using a same block portion for the logical address, and such that the matched blocks are accessible at the same time even when the matched blocks have disparate physical addresses.   
   
   
       19 . The method of  claim 18 , wherein the modified addresses are modified for writing of data to the two or more memory arrays. 
   
   
       20 . The method of  claim 18 , wherein the modified addresses are modified for reading of data to the two or more memory arrays. 
   
   
       21 . The method of  claim 18 , wherein the parameters comprise a substitute for block portion of logical addresses. 
   
   
       22 . The method of  claim 18 , wherein the parameters comprise offsets for generating the first modified addresses and the second modified addresses. 
   
   
       23 . The method of  claim 18 , wherein at least a first group of good memory blocks comprises all the good memory blocks of at least the minimum number of good memory blocks, and wherein at least a second group of good memory blocks comprises all the good memory blocks of at least the minimum number of good memory blocks.