US2009015310A1PendingUtilityA1

Semiconductor device

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Assignee: TAKAI TOMOHISAPriority: Sep 2, 2004Filed: Sep 11, 2008Published: Jan 15, 2009
Est. expirySep 2, 2024(expired)· nominal 20-yr term from priority
G11C 29/028G11C 7/20G11C 16/20G11C 29/802G11C 2029/4402
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Claims

Abstract

A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 an output circuit configured to output a first signal;   a transmission circuit including a plurality of circuit sections connected in series, each of the circuit sections including a load capacitance element that operates based on the first signal, and a buffer circuit serving to supply the first signal to subsequent ones of the circuit sections; and   a generation circuit configured to generate a pulse signal by inverting the polarity of the first signal after the first signal is transmitted to the circuit sections.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the generation circuit inverts the polarity of the first signal upon receipt of a second signal, obtained when the first signal is output from the circuit section of a last stage. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the buffer circuit includes two inverter circuits connected in series.

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