Nonvolatile semiconductor memory device which stores multi-value information

Abstract

To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

1 . A semiconductor device comprising:
 a memory including a plurality of memory cells, each of the plurality of memory cells having a storage element; and   a processing unit reading out a write data which has a plurality of bits from a buffer and transferring write information according to the write data to the memory,   wherein each of the plurality of memory cells stores the plurality of bits of the write data by setting the storage element to a first state in a first write operation or to a second state in a second write operation,   wherein in the first and second write operations, each of the plurality of memory cells are supplied a plurality of write pulses according to the write information from the processing unit, and   wherein a pulse height of a last write pulse of the plurality of write pulse is larger than a pulse height of a first write pulse of the plurality of write pulses.   
   
   
       2 . A semiconductor device according to  claim 1 , wherein the memory and the processing unit are formed on different chips. 
   
   
       3 . A semiconductor device according to  claim 1 , wherein the processing unit generates the write information by synthesizing the plurality of bits of the write data. 
   
   
       4 . A semiconductor device according to  claim 1 , wherein the memory further includes:
 a plurality of bit lines coupled to the plurality of memory cells and a plurality of sense latch circuits coupled to the plurality of bit lines, and   wherein the write information is written into one of the plurality of sense latch circuits.   
   
   
       5 . A semiconductor device according to  claim 1 , wherein the storage element is a floating gate, and
 wherein each of the plurality of memory cells further includes:   a control gate.   
   
   
       6 . A semiconductor device according to  claim 5 , wherein the memory performs a verify operation by supplying a read pulse to the control gate to read out information stored in the memory cell and comparing the information read out from the memory cell with the write information. 
   
   
       7 . A semiconductor device according to  claim 1 , wherein the memory cell is set to the second state after being set to the first state. 
   
   
       8 . A semiconductor device according to  claim 1 , wherein a pulse width of each of the plurality of write pulse is same width. 
   
   
       9 . A semiconductor device comprising:
 a memory including a plurality of memory cells, each of the plurality of memory cells having a storage element; and   a processing unit reading out a write data which has a plurality of bits from a buffer and transferring write information according to the write data to the memory,   wherein each of the plurality of memory cells stores the plurality of bits of the write data by setting the storage element to a first state in a first write operation or to a second state in a second write operation,   wherein in the first and second write operations, each of the plurality of memory cells are supplied a plurality of write pulses according to the write information from the processing unit, and   wherein a pulse width of a last write pulse of the plurality of write pulses is larger than a pulse width of a first write pulse of the plurality of write pulses.   
   
   
       10 . A semiconductor device according to  claim 9 , wherein the memory and the processing unit are formed on different chips. 
   
   
       11 . A semiconductor device according to  claim 9 , wherein the processing unit generates the write information by synthesizing the plurality of bits of the write data. 
   
   
       12 . A semiconductor device according to  claim 9 , wherein the memory further includes:
 a plurality of bits lines coupled to the plurality of memory cells and a plurality of sense latch circuits coupled to the plurality of bit lines, and   wherein the write information is written into one of the plurality of sense latch circuits.   
   
   
       13 . A semiconductor device according to  claim 9 , wherein the storage element is a floating gate, and
 wherein each of the plurality of memory cells further includes:   a control gate.   
   
   
       14 . A semiconductor device according to  claim 13 , wherein the memory performs a verify operation by supplying a read pulse to the control gate to read out information stored in the memory cell and comparing the information read out from the memory cell with the write information. 
   
   
       15 . A semiconductor device according to  claim 9 , wherein the memory cell is set to the second state after being set to the first state. 
   
   
       16 . A semiconductor device according to  claim 9 , wherein a pulse height of each of the plurality of write pulses is the same height.