Image sensor with improved dynamic range and method of formation

Abstract

Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

1 - 59 . (canceled) 
   
   
       60 . A method of fabricating a transistor, the method comprising:
 forming a semiconductor channel region; and   setting at least two threshold voltages associated with the channel region, one threshold voltage being in a sub-threshold region defined by another threshold voltage,   wherein the channel region is configured such that an exponential dependence of a drain current on an applied bias in a semi-logarithmic plot is non-linear in the sub-threshold region.   
   
   
       61 . The method of  claim 60 , wherein the transistor is formed as an active element for operating at least in part in the sub-threshold region. 
   
   
       62 . The method of  claim 60 , further comprising forming a gate for controlling the channel region; and forming first and second leads respectively coupled to a source region on one side of the channel region and a drain region on an opposite side of the channel region. 
   
   
       63 . The method of  claim 60 , wherein the act of forming the channel region comprises forming first, second, and third channel regions connected in parallel. 
   
   
       64 . The method of  claim 63 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and setting second and third threshold voltages in the sub-threshold region defined by the first threshold voltage and associated with the second and third channel regions, respectively. 
   
   
       65 . The method of  claim 63 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and setting a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the second and third channel regions. 
   
   
       66 . The method of  claim 60 , wherein the act of forming the channel region comprises forming one channel region having a normal conduction path and at least one parasitic conduction path. 
   
   
       67 . The method of  claim 66 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the normal conduction path and setting at least a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the at least one parasitic conduction path. 
   
   
       68 . The method of  claim 67 , wherein the act of forming the channel region comprises forming one channel region having first and second parasitic conduction paths, and wherein the act of setting the at least two threshold voltages comprises setting a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the first and second parasitic conduction paths. 
   
   
       69 . The method of  claim 67 , wherein the act of forming the channel region comprises forming one channel region having first and second parasitic conduction paths, and wherein the act of setting the at least two threshold voltages comprises setting second and third threshold voltages in the sub-threshold region defined by the first threshold voltage and associated with the first and second parasitic conduction paths, respectively. 
   
   
       70 . The method of  claim 60 , wherein the act of setting the two or more threshold voltages comprises forming the transistor structure having any of: two or more gate oxide thicknesses, two or more channel dopant concentrations, and two or more gate work-functions. 
   
   
       71 . The method of  claim 60 , wherein the act of setting the two or more threshold voltages comprises setting the two or more threshold voltages such that the I-V characteristic is such that the sub-threshold region and a linear region provide a same or similar amplification factor for a signal. 
   
   
       72 . The method of  claim 60 , further comprising forming a photo-conversion device. 
   
   
       73 . The method of  claim 72 , wherein the act of forming the photo-conversion device comprises forming a pinned photodiode. 
   
   
       74 . A method of forming a pixel cell, the method comprising:
 forming a photo-conversion device for producing photogenerated charges; and   forming a transistor structure coupled to the photo-conversion device, the act of forming the transistor structure comprising:
 forming at least one semiconductor channel region configured such that an exponential dependence of a drain current on an applied bias in a semi-logarithmic plot is non-linear in a sub-threshold region; 
 forming at least one gate for controlling the channel region; and 
 forming first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. 
   
   
   
       75 . The method of  claim 74 , wherein forming the channel region comprises forming first, second, and third channel regions connected in parallel and setting a highest first threshold voltage associated with the first channel region and a second threshold voltage associated with the second and third channel regions. 
   
   
       76 . The method of  claim 74 , wherein forming the channel region comprises forming first, second, and third channel regions connected in parallel and setting a highest first threshold voltage associated with the first channel region, a second threshold voltage associated with the second channel region and a third threshold voltage associated with the third channel region. 
   
   
       77 . A method of forming a pixel cell, the method comprising:
 forming a photo-conversion device; and   forming at least one transistor structure, wherein the at least one transistor structure is an active element for operating at least in part in a sub-threshold region, the act of forming the transistor structure comprising:
 forming one semiconductor channel region having a normal conduction path and at least one parasitic conduction path; 
 forming a gate for controlling the channel region; 
 forming first and second leads respectively coupled to a source region on one side of the channel region and a drain region on an opposite side of the channel region; 
 setting a highest first threshold voltage associated with the normal conduction path; and 
 setting at least a second threshold voltage associated with the at least one parasitic conduction path, 
 wherein the channel region is configured such that an exponential dependence of a drain current on an applied bias in a semi-logarithmic plot is non-linear in the sub-threshold region. 
   
   
   
       78 . The method of  claim 77 , wherein the act of forming the channel region comprises forming the normal conduction path and the at least one parasitic conduction path at the same time as a single structure. 
   
   
       79 . The method of  claim 77 , wherein the act of forming the channel region comprises forming first and second parasitic conduction paths, and wherein the act of setting the at least second threshold voltage comprises setting second and third threshold voltages associated with the first and second conduction paths, respectively.