Cache memory device and data processing method of the device

Abstract

A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.

1 . A data processing method of a cache memory device comprising:
 determining a type of data to be received; and   performing at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region, and transmitting a tail of the received data to the first cache memory region based on the determined data type.   
   
   
       2 . The method of  claim 1 , wherein the determining comprises:
 receiving a logical block address value and a sector count value; and   calculating an offset based on the received logical block address value and a super page size value, and determining the type of the data to be received based on a calculated offset and a ratio of the received sector count value to the super page size value,   wherein the performing comprises:   transmitting the head or the tail to the first cache memory region designated by a first pointer or transmitting the body to the second cache memory region designated by a second pointer based on the calculated offset and the determined data type.   
   
   
       3 . The method of  claim 1 , further comprising transmitting the body stored in the second cache memory region to an external non-volatile memory device through a channel. 
   
   
       4 . The method of  claim 2 , wherein the offset is a remainder obtained by dividing the received logical block address value by the super page size value. 
   
   
       5 . The method of  claim 2 , wherein the super page size value is obtained by multiplying a number of channels between the cache memory device and an external non-volatile memory device by a number of sectors, which is storable in a page buffer in the external non-volatile memory device. 
   
   
       6 . A data processing method of a cache memory device comprising:
 determining a data type of received data that indicates whether the received data includes a body; and   transmitting one of the received data excluding the body to a first cache memory region or transmitting the received data including the body to a second cache memory region based on the determined data type of the received data.   
   
   
       7 . The method of  claim 6 , wherein determining a data type comprises:
 receiving a logical block address value and a sector count value;   calculating an offset based on the received logical block address value and a super page size value; and   generating the data type based on the calculated offset and a ratio of the received sector count value to the super page size value.   
   
   
       8 . The method of  claim 6 , further comprising transmitting the data including the body stored in the second cache memory region to an external non-volatile memory device through a channel. 
   
   
       9 . A cache memory device comprising:
 a memory including a first cache memory region and a second cache memory region; and   a control block determining a type of data to be received and performing at least one of transmitting a head of the received data to the first cache memory region, transmitting a body of the received data to the second cache memory region, and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received.   
   
   
       10 . The device of  claim 9 , wherein the control block comprises:
 an offset calculator calculating an offset based on a logical block address value and a super page size value;   a determination unit determining the type of the data to be received based on the calculated offset and a ratio of a sector count value to the super page size value; and   a controller controlling, based on the offset calculated by the offset calculator and a determination result output from the determination unit, at least one of transmitting the head or the tail to the first cache memory region designated by a first pointer and transmitting the body to the second cache memory region designated by the second pointer.   
   
   
       11 . A cache memory device comprising:
 a memory including a first cache memory region and a second cache memory region; and   a control block determining whether data to be received includes a body, and based on the determination, transmitting received data excluding the body to a first cache memory region or transmitting the received data including the body to a second cache memory region.   
   
   
       12 . The device of  claim 11 , wherein the control block comprises:
 an offset calculator calculating an offset based on a logical block address value and a super page size value;   a determination unit determining if the data to be received includes a body based on the calculated offset and a ratio of a sector count value to the super page size value; and   a controller receiving the data, and transmitting the received data excluding the body to the first cache memory region designated by a first pointer or transmitting the received data including the body to the second cache memory region designated by a second pointer based on a determination result output from the determination unit that indicates whether the data to be received includes the body.   
   
   
       13 . A system comprising:
 a cache memory device;   a non-volatile memory device; and   a plurality of channels connected between the cache memory device and the non-volatile memory device, wherein the cache memory device comprises:
 a memory including a first cache memory region and a second cache memory region; and 
 a control block determining a type of data to be received, and controlling at least one of transmitting a head of the received data to the first cache memory region, transmitting a body of the received data to the second cache memory region, and transmitting a tail of the received data to the first cache memory region based on a type of the received data, 
 wherein the control block transmits the body stored in the second cache memory region to the non-volatile memory device through at least one of the plurality of channels. 
   
   
   
       14 . The system of  claim 13 , wherein the control block comprises:
 an offset calculator calculating an offset based on a logical block address value and a super page size value;   a determination unit determining the type of the data to be received based on the calculated offset and a ratio of a sector count value to the super page size value; and   a controller controlling at least one of transmitting the head or the tail to the first cache memory region designated by a first pointer and transmitting the body to the second cache memory region designated by the second pointer based on the offset calculated by the offset calculator and a determination result output from the determination unit that indicates the determined type of the data.   
   
   
       15 . A system comprising:
 a cache memory device;   a non-volatile memory device; and   a plurality of channels connected between the cache memory device and the non-volatile memory device, wherein the cache memory device comprises:
 a memory including a first cache memory region and a second cache memory region; and 
 a control block determining if data to be received includes a body, and transmitting received data excluding the body to a first cache memory region or transmitting the received data including the body to a second cache memory region based on a result of the determining, 
 wherein the control block transmits the data including the body stored in the second cache memory device to the non-volatile memory device through at least one of the plurality of channels. 
   
   
   
       16 . The system of  claim 15 , wherein the control block comprises:
 an offset calculator calculating an offset based on a logical block addressing value and a super page size value;   a determination unit determining if the data to be received includes a body based on the calculated offset and a ratio of a sector count value to the super page size value; and   a controller receiving the data, and transmitting the received data excluding the body to the first cache memory region designated by a first pointer or transmitting the received data including the body to the second cache memory region designated by a second pointer based on a result output from the determination unit.