Formation of lateral trench fets (field effect transistors) using steps of ldmos (lateral double-diffused metal oxide semiconductor) technology

Abstract

A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate.

1 . A semiconductor structure, comprising:
 (a) a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface;   (b) a first transistor on the semiconductor substrate; and   (c) a second transistor on the semiconductor substrate,
 wherein a first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped Source/Drain portion of the second transistor in the reference direction are essentially the same, 
 wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, 
 wherein a first gate electrode region of the first transistor is on a first side of the top substrate surface, 
 wherein a second gate electrode region of the second transistor is on a second side of the top substrate surface, and 
 wherein the first side and the second side are opposite sides of the top substrate surface. 
   
   
   
       2 . The structure of  claim 1 ,
 wherein the first doped transistor region of the first transistor has a first depth in the reference direction,   wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, and   wherein the first depth is essentially equal to the second depth.   
   
   
       3 . The structure of  claim 1 ,
 wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction,   wherein the second gate electrode region of the second transistor has a third depth in the reference direction, and   wherein the third depth is greater than the second depth.   
   
   
       4 . The structure of  claim 1 ,
 wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction,   wherein the second gate electrode region of the second transistor has a fourth depth in the reference direction, and   wherein the fourth depth is less than the second depth.   
   
   
       5 . A semiconductor structure fabrication method, comprising:
 providing a semiconductor structure which includes a semiconductor substrate,
 wherein the semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface; 
   simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate,
 wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, 
 wherein the first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity; and 
   forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate,
 wherein the second gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the second gate electrode region and the semiconductor substrate. 
   
   
   
       6 . The method of  claim 5 , further comprising forming a first gate dielectric layer and a first gate electrode region of the second transistor on the semiconductor substrate,
 wherein the first gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the first gate electrode region and the semiconductor substrate,   wherein a first gate electrode region of the first transistor is on a first side of the top substrate surface,   wherein a second gate electrode region of the second transistor is on a second side of the top substrate surface, and   wherein the first side and the second side are opposite sides of the top substrate surface.   
   
   
       7 . The method of  claim 5 , wherein said simultaneously forming the first doped transistor region and the first doped Source/Drain portion comprises implanting dopants in the semiconductor substrate by ion implantation. 
   
   
       8 . The method of  claim 5 ,
 wherein the first doped transistor region of the first transistor has a first depth in the reference direction,   wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction, and   wherein the first depth is essentially equal to the second depth.   
   
   
       9 . The method of  claim 5 , further comprising simultaneously forming a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate,
 wherein the second doped transistor region and the second doped Source/Drain portion comprise dopants of the first doping polarity, and   wherein the second doped Source/Drain portion is in direct physical contact with the first doped Source/Drain portion.   
   
   
       10 . The method of  claim 9 , wherein said simultaneously forming the second doped transistor region and the second doped Source/Drain portion comprises implanting dopants in the semiconductor substrate by ion implantation. 
   
   
       11 . The method of  claim 9 , further comprising forming a third doped transistor region of the first transistor on the semiconductor substrate,
 wherein the third doped transistor region comprises dopants of a second doping polarity which is opposite to the first doping polarity.   
   
   
       12 . The method of  claim 11 , further comprising simultaneously forming a fourth doped transistor region of the first transistor and a fourth doped Source/Drain portion of the second transistor on the semiconductor substrate,
 wherein the fourth doped transistor region and the fourth doped Source/Drain portion comprise dopants of the first doping polarity, and   wherein the fourth doped Source/Drain portion is in direct physical contact with the second doped Source/Drain portion.   
   
   
       13 . The method of  claim 12 , wherein said simultaneously forming the fourth doped transistor region and the fourth doped Source/Drain portion comprises implanting dopants in the semiconductor substrate by ion implantation. 
   
   
       14 . The method of  claim 12 , further comprising simultaneously forming a fifth doped transistor region of the first transistor and a fifth doped Source/Drain portion of the second transistor on the semiconductor substrate,
 wherein the fifth doped transistor region and the fifth doped Source/Drain portion comprise dopants of the first doping polarity, and   wherein the fifth doped Source/Drain portion is in direct physical contact with the fourth doped Source/Drain portion.   
   
   
       15 . The method of  claim 5 , wherein said forming the second gate dielectric layer and the second gate electrode region is performed before said simultaneously forming the first doped transistor region and the first doped Source/Drain portion is performed. 
   
   
       16 . The method of  claim 15 ,
 wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction,   wherein the second gate dielectric layer of the second transistor has a third depth in the reference direction, and   wherein the third depth is greater than the second depth.   
   
   
       17 . The method of  claim 15 , further comprising, after said forming the second gate dielectric layer and the second gate electrode region is performed, forming a shallow trench isolation (STI) region on the semiconductor substrate,
 wherein the STI region is in direct physical contact with the second gate dielectric layer and the second gate electrode region.   
   
   
       18 . The method of  claim 5 , wherein said forming the second gate dielectric layer and the second gate electrode region is performed after said simultaneously forming the first doped transistor region and the first doped Source/Drain portion is performed. 
   
   
       19 . The method of  claim 18 ,
 wherein the first doped Source/Drain portion of the second transistor has a second depth in the reference direction,   wherein the second gate dielectric layer of the second transistor has a fourth depth in the reference direction, and   wherein the fourth depth is less than the second depth.   
   
   
       20 . The method of  claim 18 , further comprising, before said forming the second gate dielectric layer and the second gate electrode region is performed, forming a shallow trench isolation (STI) region on the semiconductor substrate,
 wherein the STI region is in direct physical contact with the second gate dielectric layer.