Low-Power Integrated-Circuit Signal Processor With Wide Dynamic Range

Abstract

An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.

1 . An integrated circuit containing at least one analog circuitry section for producing a final analog output information signal in response to a first analog input information signal, comprising:
 a first analog circuitry subsection that produces an intermediate analog output voltage in response to said first analog input information signal;   a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output voltage and produces said final output information signal in response to said intermediate analog input current;   a first power-supply-voltage terminal coupled to said first analog circuitry subsection;   a second power-supply-voltage terminal coupled to said second analog circuitry subsection; and   a third power-supply-voltage terminal coupled to said first analog circuitry subsection and said second analog circuitry subsection;   wherein the available dynamic range of said intermediate analog output voltage is designed to exceed the difference in voltage applied between said second and third power-supply terminals.   
     
     
         2 . An integrated circuit according to  claim 1 , wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a negative voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a negative voltage is applied to the second power-supply terminal with respect to said third power-supply terminal. 
     
     
         3 . An integrated circuit according to  claim 2 , including a capacitive voltage inverter for producing a negative power supply voltage in response to a positive power supply voltage applied to said third power-supply-voltage terminal wherein said negative power supply voltage is connected to said first power-supply-voltage terminal. 
     
     
         4 . An integrated circuit according to  claim 1 , wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a positive voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a positive voltage is applied to the second power-supply terminal with respect to said third power-supply terminal. 
     
     
         5 . An integrated circuit according to  claim 4 , including a charge pump means producing a first positive power supply voltage in response to a second positive power supply applied to said second power-supply-voltage terminal wherein said first power supply voltage is connected to said first power-supply-voltage terminal, and where said first positive power supply voltage is greater than said second power supply voltage. 
     
     
         6 . An integrated circuit according to  claim 1 , wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current. 
     
     
         7 . An integrated circuit according to  claim 1 , wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, and said final analog output voltage is substantially less in total excursion than said intermediate output voltage. 
     
     
         8 . An integrated circuit according to  claim 1 , wherein said second analog subsection produces a final analog voltage or current that is a syllabically compressed version of said intermediate output voltage. 
     
     
         9 . An integrated circuit according to  claim 8 , wherein said second analog subsection includes:
 a variable gain means for producing said final analog output voltage in response to said intermediate input current; and   a level detector means for producing a gain control signal in response to said final analog output voltage;   wherein the gain of said variable gain means responds to said gain control signal such that said gain is decreased in response to an increase in said final analog output voltage or current and said gain is increased in response to a decrease in said final analog output voltage or current.   
     
     
         10 . An integrated circuit according to  claim 8 , wherein said second analog subsection includes:
 a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and   a level detector for producing a gain control signal in response to said final analog output voltage;   wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said intermediate input current and said gain is increased in response to a decrease in said intermediate input current.   
     
     
         11 . An integrated circuit containing at least one analog circuitry section for producing a final analog output information signal in response to a first analog input information signal, comprising:
 a first analog circuitry subsection that produces an intermediate analog output voltage in response to said first analog input information signal;   a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output voltage and produces said final output information signal in response to said intermediate analog input current;   a first positive power-supply-voltage terminal coupled to said first analog circuitry subsection;   a second positive power-supply-voltage terminal coupled to said second analog circuitry subsection;   a first negative power-supply-voltage terminal coupled to said first analog circuitry subsection; and   a second negative power-supply-voltage terminal coupled to said second analog circuitry subsection;   wherein the available dynamic range of said intermediate output voltage is designed to exceed the difference in voltage between said second positive and second negative power-supply terminals.   
     
     
         12 . An integrated circuit according to  claim 11 , wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current. 
     
     
         13 . An integrated circuit according to  claim 11 , wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, and said final analog output voltage is substantially less in total excursion than said intermediate output voltage. 
     
     
         14 . An integrated circuit according to  claim 13 , wherein said second analog subsection is configured so as to produce an analog output current in response to said intermediate analog input current. 
     
     
         15 . An integrated circuit according to  claim 13 , wherein said second analog subsection is configured so as to produce a final analog output voltage in response to said intermediate analog input current, wherein said final analog output voltage is substantially less in total excursion than said intermediate output voltage. 
     
     
         16 . An integrated circuit according to  claim 11 , wherein said second analog subsection is configured so as to produce a final analog voltage or current that is a syllabically compressed version of said intermediate output voltage. 
     
     
         17 . An integrated circuit according to  claim 16 , wherein said second analog subsection includes:
 a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and   a level detector for producing a gain control signal in response to said final analog output voltage;   wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said final analog output voltage or current and said gain is increased in response to a decrease in said final analog output voltage or current.   
     
     
         18 . An integrated circuit according to  claim 16 , wherein said second analog subsection includes:
 a variable gain stage for producing said final analog output voltage in response to said intermediate input current; and   a level detector for producing a gain control signal in response to said final analog output voltage;   wherein the gain of said variable gain stage responds to said gain control signal such that said gain is decreased in response to an increase in said intermediate input current and said gain is increased in response to a decrease in said intermediate input current.   
     
     
         19 . An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal. 
     
     
         20 . An integrated circuit containing at least one analog circuitry section for producing a final analog output voltage in response to a first analog input information signal, comprising:
 a first analog circuitry subsection that produces an intermediate analog output current in response to said first analog input information signal;   a second analog circuitry subsection that accepts an intermediate analog input current proportional to said intermediate output current and produces said final output voltage in response to said intermediate analog input current;   a first power-supply-voltage terminal coupled to said first analog circuitry subsection;   a second power-supply-voltage terminal coupled to said second analog circuitry subsection; and   a third power-supply-voltage terminal coupled to said first analog circuitry subsection and said second analog circuitry subsection;   wherein the available dynamic range of said final analog output voltage is designed to exceed the difference in voltage applied between said first and third power-supply terminals.   
     
     
         21 . An integrated circuit according to  claim 20 , wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a negative voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a negative voltage is applied to the second power-supply terminal with respect to said third power-supply terminal. 
     
     
         22 . An integrated circuit according to  claim 21 , including a capacitive voltage inverter for producing a negative power supply voltage in response to a positive power supply voltage applied to said third power-supply-voltage terminal wherein said negative power supply voltage is connected to said second power-supply-voltage terminal. 
     
     
         23 . An integrated circuit according to  claim 20 , wherein said first analog circuitry subsection, first power-supply-voltage terminal and said third power-supply-voltage terminal are configured so that in operation a positive voltage is applied to the first power-supply-voltage terminal with respect to said third power-supply-voltage terminal, and said second analog circuitry subsection, second power-supply-voltage terminal and third power-supply-voltage are configured so that in operation a positive voltage is applied to the second power-supply terminal with respect to said third power-supply terminal. 
     
     
         24 . An integrated circuit according to  claim 23 , including a charge pump means producing a second positive power supply voltage in response to a first positive power supply applied to said first power-supply-voltage terminal wherein said second power supply voltage is connected to said second power-supply-voltage terminal, and where said second positive power supply voltage is greater than said first power supply voltage. 
     
     
         25 . An integrated circuit according to  claim 20 , wherein said first analog subsection produces an intermediate analog current that is a syllabically expanded version of said first analog input information signal. 
     
     
         26 . An integrated circuit according to  claim 25 , wherein said first analog subsection includes:
 a variable gain means for producing said intermediate analog current in response to first analog input information signal; and   a level detector means for producing a gain control signal in response to said first analog input information signal;   wherein the gain of said variable gain means responds to said gain control signal such that said gain is increased in response to an increase in said first analog input information signal and said gain is decreased in response to a decrease in said first analog input information signal.