Efficient image transmission between TV chipset and display device

Abstract

Compression and decompression with high image quality is applied to reduce the data rate of transmitting an image results in high efficiency image transmission between TV and display device is presented. An LVDS bus is hooked between the TV side and display device with this invention of image compression apparatus in the TV side to reduce data rate and image decompression in the display device to reconstruct the image to be displayed.

1 . An apparatus of image data transmission between television subsystem and display subsystem, comprising:
 a TV chipset unit functioning at least features as program tuning and selection, video and audio decompression, and in the video feature: de-interlacing and frame rate conversion from the received number of field or frame to the predetermined frame rate per second, constructing the frame images by referring to the accessed adjacent filed/frame pixels;   an image compression unit embedded in the TV side reduces the data rate of the decompressed and processed video images;   a pixel bus with transmission unit embedded in the TV side to submit the compressed image to the display device;   a pixel bus with receiving unit embedded in the side of display device to receive the compressed image;   An image decompression unit embedded in the display device reconstructs the received images previously compressed in the TV side and temporarily saves the decompressed image into a frame buffer storage device and waits for the predetermined right timing to be sent to the display unit; and   a display unit with pixel driving unit for accurately driving out the corresponding pixels to the predetermined points of a display unit.   
   
   
       2 . The apparatus of  claim 1 , wherein the video decompression unit referring to adjacent field or frame of pixels will have another still image compression codec to compress the image before saving into the temporary buffer as referencing frames and to decompress the accessed pixels before being used as reference. 
   
   
       3 . The apparatus of  claim 1 , wherein the video de-interlacing referring to adjacent field or frame of pixels will have another still image compression codec to compress the image before saving into the temporary buffer as referencing frames and to decompress the accessed pixels before being used as reference. 
   
   
       4 . The apparatus of  claim 1 , wherein the frame rate conversion unit referring to adjacent field or frame of pixels will have another still image compression codec to compress the image before saving into the temporary buffer as referencing frames and to decompress the accessed pixels before being used as reference. 
   
   
       5 . The apparatus of  claim 1 , wherein the pixel bus for transmitting and receiving pixels of image is comprised of a predetermined voltage level of data signal swing to represent the logic “0” or “1” with referencing signal submitting together with the pixel data line to differentiate logic signal “0” and “1”. 
   
   
       6 . The apparatus of  claim 1 , wherein the pixel bus for transmitting and receiving pixels of image is an LVDS. Low Voltage Differential Signal bus with low signal swing between logic “0” and “1”. 
   
   
       7 . The apparatus of  claim 1 , wherein the image data are compressed and putting to the LVDS bus for transmission and are decompressed in the receiver terminal before sending to the display controller. 
   
   
       8 . An apparatus of image data transmission between television subsystem and display subsystem, comprising:
 a TV chipset unit functioning at least features as program tuning and selection, video and audio decompression, and in the video feature: de-interlacing and frame rate conversion from the received number of field or frame to the predetermined frame rate per second, constructing the frame images by referring to the accessed adjacent filed/frame pixels;   a pixel bus with transmission unit embedded in the TV side to submit the decompressed and processed images to the display device;   a pixel bus with receiving unit embedded in the side of display device to receive the decompressed and processed images sent from the TV side;   a control unit in the display device determines the timing of presenting the corresponding pixels to the display driver with an image compression and decompression unit, compressing the image before temporarily saving to the pixel buffer and decompressing the frame pixels accessed from the temporary pixel buffer before sending to the display driving devices; and   a display unit with pixel driving devices for accurately driving out the corresponding pixels to the predetermined points of the display unit.   
   
   
       9 . The apparatus of  claim 8 , wherein in the display device, the compression unit is embedded in the display timing control unit and reduces the pixels data rate of an image before saving into a temporary pixel buffer. 
   
   
       10 . The apparatus of  claim 8 , wherein in the display device, the decompression unit is embedded in the display timing control unit and reconstructs the pixels of an image line by line before sending into the display drivers. 
   
   
       11 . The apparatus of  claim 8 , wherein in the display device, when integrating the compression unit into the timing controller, the temporary pixel buffer memory density is reduced. 
   
   
       12 . The apparatus of  claim 8 , wherein in the display device, when integrating the compression unit into the timing controller, the temporary pixel buffer memory I/O bus width is reduced by a factor of at least two. 
   
   
       13 . An apparatus of image data transmission between television subsystem and display subsystem, comprising:
 a TV chipset unit functioning at least features as program tuning and selection, video and audio decompression, and in the video point: de-interlacing and frame rate conversion from the received number of field or frame to the predetermined frame rate per second, constructing the frame images by referring to the accessed adjacent filed/frame pixels;   a pixel bus with transmission unit embedded in the TV side to submit the decompressed and processed images to the display device;   a pixel bus with receiving unit embedded in the side of display device to receive the decompressed and processed images sent from the TV side;   a control unit in the display device determines the timing of presenting the corresponding pixels to the display driver with an image compression unit which compresses the image before temporarily saving to the pixel buffer; and   a display unit with pixel driving devices with image decompression unit embedded in each corresponding display driving device to decompressing the corresponding lines of pixels for accurately driving out the corresponding reconstructed pixels to the predetermined points of the display unit.   
   
   
       14 . The apparatus of  claim 13 , wherein in the display driver side, at least one line buffer is built inside each of the display driver and a decompression unit recovers a whole line of pixels to be driven out to the display device. 
   
   
       15 . The apparatus of  claim 13 , wherein in the display driver, the decompression unit is embedded in the display driver which receives a compressed line of pixels from the display timing control unit and decompresses the line pixels and drives out pixels of an image line by line to the display device. 
   
   
       16 . The apparatus of  claim 13 , wherein in the display driver, the decompression unit embedded inside the display driver reconstructs the corresponding lines of pixels and drives out the pixels to the corresponding location of the display device. 
   
   
       17 . The apparatus of  claim 13 , wherein in the display device, when integrating the compression unit into the timing controller and the decompression unit into the display drivers, the temporary pixel buffer memory density is reduced by a factor of at least two. 
   
   
       18 . The apparatus of  claim 13 , wherein in the display device, when integrating the compression unit into the timing controller and the decompression unit into the display drivers, the temporary pixel buffer memory I/O bus width is reduced by a factor of at least two. 
   
   
       19 . The apparatus of  claim 13 , wherein in the TV side, a compression unit reduces the data rate of the image and sends through a pixel us to the display unit, and the compressed image pixels are temporarily saved in a frame buffer till the decompression unit in the display driver reconstructs the pixels and drives them out to the corresponding location of a display device.