Interconnection process

Abstract

An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.

1 . An interconnection process, comprising:
 providing a substrate having a conductive region;   forming a dielectric layer on the substrate;   forming a patterned metal hard mask layer having a trench opening on the dielectric layer;   conformally forming a dielectric hard mask layer on the patterned metal hard mask layer and filled in the trench opening;   defining a photoresist pattern to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer in the trench opening to form a first opening in the dielectric layer;   removing the photoresist pattern;   performing a first etching process with use of the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer in the range of the trench opening of the patterned metal hard mask layer, wherein the second opening exposes the conductive region; and   forming a conductive layer in the trench and in the second opening.   
     
     
         2 . The interconnection process of  claim 1 , wherein the material of the dielectric hard mask layer comprises silicon oxide. 
     
     
         3 . The interconnection process of  claim 1 , wherein the material of the patterned metal hard mask layer comprises titanium nitride (TiN), tantalum nitride (TaN) or a titanium-tungsten alloy. 
     
     
         4 . The interconnection process of  claim 1 , wherein the conductive region comprises a conductive wire or an electrode. 
     
     
         5 . The interconnection process of  claim 1 , wherein the material of the dielectric layer comprises the dielectric material with low dielectric constant. 
     
     
         6 . The interconnection process of  claim 1 , wherein the material of the conductive layer comprises copper or tungsten. 
     
     
         7 . The interconnection process of  claim 1 , wherein a method of forming the first opening comprises:
 forming a patterned photoresist layer on the dielectric hard mask layer,   performing a second etching process with use of the patterned photoresist layer as a mask to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer; and   removing the patterned photoresist layer.   
     
     
         8 . The interconnection process of  claim 1 , wherein a cap layer is further formed on the substrate before the step of forming the dielectric layer. 
     
     
         9 . The interconnection process of  claim 1 , wherein a polishing stop layer or a glue layer is further formed on the dielectric layer after the dielectric layer is formed and before the patterned metal hard mask layer is formed. 
     
     
         10 . The interconnection process of  claim 1 , wherein a method of forming the conductive layer comprises:
 forming a conductive material layer over the substrate; and   performing a planarization process to remove the conductive material layer outside the trench and the second opening.   
     
     
         11 - 21 . (canceled)