High data rate serial peripheral interface

Abstract

An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

1 . A serial peripheral interface for use with a central processing unit (CPU); a bus interface in communication with the CPU; a CPU memory module in communication with the bus interface; the CPU memory module configured to include a FIFO memory buffer; and a direct memory access module in communication with the bus interface; comprising:
 the serial peripheral interface (SPI) in communication with the direct memory access module and the bus interface;   the serial peripheral interface having SPI hardware configured to maintain pointers to addresses within the FIFO memory buffer;   the SPI hardware configured to maintain counters; and   the serial peripheral interface configured to use the FIFO memory buffer, pointers and counters as a transmission buffer for external communications for creating a virtual special function register.   
   
   
       2 . The serial peripheral interface of  claim 1 , further comprising a transmitter buffer and a receiver buffer; wherein the transmitter buffer is configured to transmit data from the FIFO memory buffer, and wherein the receiver buffer is configured to transmit data to the FIFO memory buffer. 
   
   
       3 . The serial peripheral interface of  claim 1 , further configured to operate as one of a master device and a slave device. 
   
   
       4 . The serial peripheral interface of  claim 1 , further configured to provide a data register chip select signal. 
   
   
       5 . The serial peripheral interface of  claim 1 , further configured to provide at least one of a CPU transmitter pointer signal, a CPU receiver pointer signal, a SPI transmitter pointer signal and a SPI receiver pointer signal. 
   
   
       6 . The serial peripheral interface of  claim 1 , wherein the serial peripheral interface is further configured to communicate with the DMA module and the bus interface for providing cycle stealing. 
   
   
       7 . The serial peripheral interface of  claim 6 , wherein the SPI hardware further comprises:
 a plurality of hardware pointers to memory locations in a FIFO buffer; at least one hardware pointer counter; and   a hardware logic device; wherein the hardware logic device is configured to communicate with the bus interface and to utilize the FIFO buffer for intermediate storage of data being transmitted from and received to the CPU.   
   
   
       8 . The serial peripheral interface of  claim 7 , wherein the plurality of hardware pointers are configured to provide at least one of a CPU transmitter pointer signal, a CPU receiver pointer signal, a SPI transmitter pointer signal and a SPI receiver pointer signal. 
   
   
       9 . The serial peripheral interface of  claim 7 , further comprising a transmitter buffer and a receiver buffer; wherein the transmitter buffer is configured to transmit data from the FIFO buffer, and wherein the receiver buffer is configured to transmit data to the FIFO buffer. 
   
   
       10 . The serial peripheral interface of  claim 7 , further configured to operate as one of a master device and a slave device. 
   
   
       11 . The serial peripheral interface of  claim 1 , further configured to provide a data register chip select signal to the bus interface.