Self-biasing transistor structure and an sram cell having less than six transistors

Abstract

By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

1 .- 11 . (canceled) 
   
   
       12 . A transistor element, comprising:
 a drain region;   a source region;   a channel region formed between said drain region and said source region and being configured to define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the channel region into a low impedance state and a second threshold voltage of the semiconductor device that results in a first abrupt conductivity change of the total conductivity of said channel region when said total conductivity is in the low impedance state; and   a gate electrode located to control said channel region by capacitive coupling.   
   
   
       13 . The transistor element of  claim 12 , wherein said first abrupt conductivity change is defined for an absolute amount of gate voltage that maintains said channel region in a low impedance state to define a local maximum of the conductivity with respect to said absolute amount. 
   
   
       14 . The transistor element of  claim 12 , wherein said channel region comprises at least a first channel sub-region having a first conductivity type and a second channel sub-region having a second conductivity type that differs from the first conductivity type. 
   
   
       15 . The transistor element of  claim 14 , wherein said first conductivity type of said first channel sub-region differs from a conductivity type of said drain and source regions, said first channel sub-region being located more closely to said gate electrode than said second channel sub-region. 
   
   
       16 . The transistor element of  claim 12 , further comprising a doped semiconductor region having a conductivity type and being located adjacent to said drain region, source region and said channel region, said conductivity type differing from a conductivity type of said drain region and source region. 
   
   
       17 . The transistor element of  claim 12 , further comprising an insulation layer formed adjacent to said drain and source regions and said channel region, said insulation layer isolating said transistor element from a substrate. 
   
   
       18 . The transistor element of  claim 14 , wherein said first and second channel sub-regions differ in at least one of material composition and internal strain. 
   
   
       19 . A static RAM cell, comprising:
 a select transistor; and   an information storage element coupled to said select transistor, said information storage element including less than four transistor elements, wherein one of the transistor elements comprises a first controllable semiconductor device including at least:
 a drain region; 
 a source region; 
 a channel region formed between said drain region and said source region and being configured to define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the channel region into a low impedance state and a second threshold voltage of the semiconductor device that results in a first abrupt conductivity change of the total conductivity of said channel region when said total conductivity is in the low impedance state; and 
 a gate electrode located to control said channel region by capacitive coupling. 
   
   
   
       20 . The static RAM cell of  claim 19 , wherein said controllable semiconductor device has at least one stationary conductive state and wherein said channel region is connected to said gate electrode and configured to self-bias said gate electrode when said semiconductor device is in said at least one stationary conductive state. 
   
   
       21 . The static RAM cell of  claim 20 , wherein
 said channel region is configured to define at least a first threshold for an absolute amount of voltage applied to the gate electrode, said first threshold being a lower limit for a gate voltage to transit into said self-biased at least one stationary conductive state.   
   
   
       22 . The static RAM cell of  claim 21 , wherein said channel region comprises at least a first channel sub-region having a first conductivity type and a second channel sub-region having a second conductivity type that differs from the first conductivity type. 
   
   
       23 . The static RAM cell of  claim 22 , wherein said first conductivity type of said first channel sub-region differs from a conductivity type of said drain and source regions, said first channel sub-region being located more closely to said gate electrode than said second channel sub-region. 
   
   
       24 . The static RAM cell of  claim 21 , wherein said controllable semiconductor device further comprises a doped semiconductor region having a conductivity type and being located adjacent to said drain region, source region and said channel region, said conductivity type differing from a conductivity type of said drain region and source region. 
   
   
       25 . The static RAM cell of  claim 21 , wherein said controllable semiconductor device further comprises an insulation layer formed adjacent to said drain and source regions and said channel region, said insulation layer isolating said semiconductor device from a substrate. 
   
   
       26 . The static RAM cell of  claim 23 , wherein said first and second channel sub-regions differ in at least one of material composition and internal strain. 
   
   
       27 . The static RAM cell of  claim 19 , wherein said information storage element comprises a second controllable semiconductor device having at least one stationary conductive state and having a second channel region and a second gate electrode configured to control a conductivity of said second channel region, said second channel region connected to said second gate electrode and being configured to self-bias said second gate electrode when said semiconductor device is in said at least one stationary conductive state. 
   
   
       28 . The static RAM cell of  claim 27 , wherein said second controllable semiconductor device is operable in a self-biased state with a second control voltage that differs from a first control voltage required to operate said controllable semiconductor device in a self-biased state. 
   
   
       29 . A static RAM cell, comprising:
 a transistor element having a gate electrode, a drain region, a source region, a channel region formed between said drain region and said source region and electrically connected with said gate electrode and controllable by said gate electrode, said transistor element being configured to define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the channel region into a low impedance state and a second threshold voltage of the semiconductor device that results in a first abrupt conductivity change of the total conductivity of said channel region when said total conductivity is in the low impedance state and self-bias said gate electrode to maintain said channel region in a stationary conductive state.   
   
   
       30 . The static RAM cell of  claim 29 , further comprising a select transistor element coupled to said transistor element. 
   
   
       31 . The static RAM cell of  claim 30 , wherein a total number of transistor elements is less than six. 
   
   
       32 . The static RAM cell of  claim 29 , wherein said channel region is formed between said drain region and said source region and is configured to define at least a first threshold for an absolute amount of voltage applied to the gate electrode, said first threshold being a lower limit for a gate voltage to transit into said self-biased stationary conductive state. 
   
   
       33 . The static RAM cell of  claim 32 , wherein said channel region comprises at least a first channel sub-region having a first conductivity type and a second channel sub-region having a second conductivity type that differs from the first conductivity type. 
   
   
       34 . The static RAM cell of  claim 33 , wherein said first conductivity type of said first channel sub-region differs from a conductivity type of said drain and source regions, said first channel sub-region being located more closely to said gate electrode than said second channel sub-region. 
   
   
       35 . The static RAM cell of  claim 29 , wherein said transistor element further comprises a doped semiconductor region having a conductivity type and being located adjacent to said drain region, source region and said channel region, said conductivity type differing from a conductivity type of said drain region and source region. 
   
   
       36 . The static RAM cell of  claim 29 , wherein said transistor element further comprises an insulation layer formed adjacent to said drain and source regions and said channel region, said insulation layer isolating said transistor element from a substrate. 
   
   
       37 . The static RAM cell of  claim 33 , wherein said first and second channel sub-regions differ in at least one of material composition and internal strain. 
   
   
       38 . The static RAM cell of  claim 29 , further comprising a second transistor element having at least one self-biased stationary conductive state and having a second channel region and a second gate electrode configured to control a conductivity of said second channel region, said second channel region connected to said second gate electrode and being configured to self-bias said second gate electrode when said transistor element is in said at least one self-biased stationary conductive state. 
   
   
       39 . A static RAM cell comprising two or less transistor elements, wherein at least one of the two or less transistor elements comprises:
 a drain region;   a source region;   a channel region formed between said drain region and said source region and being configured to define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the channel region into a low impedance state and a second threshold voltage of the semiconductor device that results in a first abrupt conductivity change of the total conductivity of said channel region when said total conductivity is in the low impedance state; and   a gate electrode located to control said channel region by capacitive coupling.   
   
   
       40 . The static RAM cell of  claim 39 , wherein at least one of the two or less transistor elements is a double channel transistor element. 
   
   
       41 . The static RAM cell of  claim 40 , wherein said double channel transistor element comprises:
 a drain region formed in a substantially crystalline semiconductor material and doped to provide a first conductivity type;   a source region formed in said substantially crystalline semiconductor material and doped to provide the first conductivity type;   a first channel region located between said drain region and said source region and doped to provide the first conductivity type; and   a second channel region located between said drain region and said source region and adjacent to the first channel region and being doped to provide a second conductivity type differing from said first conductivity type.