Coder and a method of coding for codes having a repeated maximum transition run constraint of 2

Abstract

Presently known codes have long trains consisting of consecutive 2T runs that reduce the performance of the bit detector. By using a code with an RMTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an RMTR constraint of 2 is presented. Several variations of such a code are disclosed where one or more sub-codes are used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index T max +1−t.

1 . A method of converting a user bitstream into a coded bitstream by means of an overall channel code comprising the steps of
 converting M-bit information words into N-bit code words,   realizing said overall channel code by concatenating a number S of sub-codes in a cyclically repeated order with a predetermined repeat period, wherein each of the sub-codes receives m i -bit information words, where m i  is an integer characteristic for each of the sub-codes, that are converted into n i -bit code words, where n i  is an integer characteristic for each of the sub-codes, and where for each sub-code, said characteristic integer number n i  is greater than said characteristic integer number m i , such that the sum of the m i -numbers of all sub-codes within said repeat period equals M, and that the sum of the n, -numbers of all sub-codes within said repeat period equals N, and:   logically or physically dividing for each sub-code, its n i -bit code words into a number of T max  different code-word types and logically or physically arranging its n i -bit code words into T max  coding classes of coding states such that, for a given sub-code, an n i -bit code word of type t, where t is an integer number between 1 and T max , can be concatenated into a concatenated set of code words, realizing said N i+1 -bit code-words of said overall channel code that generates said coded bitstream, with an n i+1 -bit code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index T max +1−t.   
   
   
       2 . A method as claimed in  claim 1 , where the code-word type is determined by a number of trailing bits of said code-word. 
   
   
       3 . A method as claimed in  claim 1 , where the code-word type is determined by all bits of said code-word, together with at least one bit of a preceding code-word. 
   
   
       4 . A method as claimed in  claim 2 , wherein the concatenated set of N-bit code words realizing said coded bitstream satisfy a dkr-constraint, where d refers to a minimum number of zero-bits between two consecutive one-bits in the coded bitstream, and k refers to a maximum number of zero-bits between two consecutive one-bits in the coded bitstream, and where r indicates a maximum number of consecutive minimum runs of d zero-bits each preceded by a one-bit. 
   
   
       5 . A method as claimed in  claim 4 , where the number of different code-word types  T  and non-empty coding classes, wherein a non-empty coding class is defined to have at least one coding state, is not larger than T max =1+(d+1)×(r+1). 
   
   
       6 . A method as claimed in  claim 4 , where the number of different code-word types T and the number of different non-empty coding classes T, where T equals T max =1+(d+1)×(r+1). 
   
   
       7 . A method as claimed in  claim 5 , where d=1 and r=2, and T max  equals 7. 
   
   
       8 . A method as claimed in  claim 7 , where T=T max 7 and where the number of sub-codes S equals 6. 
   
   
       9 . A method as claimed in  claim 8 , where one of the sub-codes has a mapping with m=8 and n=11, and the other sub-codes have a mapping with m=8 and n=12. 
   
   
       10 . A method as claimed in  claim 7 , where T=T max =7 and where the number of sub-codes S equals 3. 
   
   
       11 . A method as claimed in  claim 10 , where one of the sub-codes has m=9 and n=14, and the other sub-codes have m=9 and n=13. 
   
   
       12 . A method as claimed in  claim 7 , where T=T max =7 and where the number of sub-codes S equals 1. 
   
   
       13 . A method as claimed in  claim 12 , where the sub-code has a mapping with m=4 and n=6. 
   
   
       14 . A method as claimed in  claim 12 , where the single sub-code has a mapping with m=2 and n=3. 
   
   
       15 . A method as claimed in  claim 5 , where, for each of the sub-codes, each of said T≦T max  non-empty coding classes of coding states comprises p 1 , p 2 , . . . , p max  coding states, wherein the trivial empty coding classes are omitted, such that for the numbers representing the non-zero number of states of the non-empty coding classes p 1 ≦p 2 ≦ . . . ≦p max , and with p max  giving the total number of coding states for said considered sub-code, further characterized in that each of the p i  coding states of a given considered class “i”, is also a coding state of all classes that have an index larger than “i”. 
   
   
       16 . A method as claimed in  claim 7 , where for each sub-code trailing bits are specified for the different code word types by the following set of rules, that is,
 the n-bit code words of the 1st type end with   “00”,   the n-bit code words of the 2nd type end with   “0010”,   the n-bit code words of the 3rd type end with   
     “001010”,
 the n-bit code words of the 4th type end with 
 
     “00101010”,
 the n-bit code words of the 5th type end with 
 “001”, 
 the n-bit code words of the 6th type end with 
 “00101”, 
 the n-bit code words of the 7th type end with 
 “0010101”, 
 and where leading bits of the code words belonging to the different coding classes are determined by the following set of rules, that is, 
 the n-bit code words of a coding state of the 1st class start with 
 “00”, 
 the n-bit code words of a coding state of the 2nd class start with 
 “00” or “0100”, 
 the n-bit code words of a coding state of the 3rd class start with 
 “00”, “0100” or “010100”, 
 the n-bit code words of a coding state of the 4th class start with 
 “00”, “0100”, “010100” or “01010100”, 
 the n-bit code words of a coding state of the 5th class start with 
 “00”, “0100”, “010100”, “01010100” or “100”, 
 the n-bit code words of a coding state of the 6th class start with 
 “00”, “0100”, “010100”, “01010100”, “100” or “10100”, 
 the n-bit code words of a coding state of the 7th class start with 
 “00”, “0100”, “010100”, “01010100”, “100”, “10100” or “1010100”. 
 
   
   
       17 . A method as claimed in  claim 9 , where for the first sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =11, p 2 =15, p 3 =17, p 4 =17, p 5 =24, p 6 =27 and p 7 =28, and where for the second sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =10, p 2 =14, p 3 =15, p 4 =16, p 5 =22, p 6 =25 and p 7 =26, and where for the third sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =9, p 2 =3, p 3 =14, p 4 =14, p 5 =20, p 6 =23 and p 7 =24 and where for the fourth sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =13, p 4 =13, p 5 =19, p 6 =21 and p 7 =22 and where for the fifth sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =12, p 4 =12, p 5 =17, p 6 =19 and p 7 =20 and where for the sixth sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =12, p 5 =16, p 6 =18 and p 7 =19. 
   
   
       18 . A method as claimed in  claim 11 , where for the first sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =11, p 5 =16, p 6 =18 and p 7 =19, and where for the second sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =12, p 3 =13, p 4 =13, p 5 =19, p 6 =21 and p 7 =22, and where for the third sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =10, p 2 =14, p 3 =15, p 4 =16, p 5 =22, p 6 =25 and p 7 =26. 
   
   
       19 . A method as claimed in  claim 13 , where the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =3, p 2 =4, p 3 =5, p 4 =5, p 5 =7, p 6 =8 and p 7 =8. 
   
   
       20 . A method as claimed in  claim 19 , where a finite k-constraint is realized through an extra coding state. 
   
   
       21 . A method as claimed in  claim 14 , where a number of non-trivial coding classes T equals 6, with coding class number 4 being the empty one, yielding p 4 =0 and where the number p 1 , p 2 , p 3 , p 5 , p 6 , p 7  of coding states for each of the non-trivial coding classes T of coding states amounts to p 1 =2, p 2 =2, p 3 =3, p 5 =4, p 6 =5 and p 6 =5. 
   
   
       22 . A method as claimed in claim- 21 , where a parity-preserve property is realized through at least one extra coding state. 
   
   
       23 . A method as claimed in  claim 21 , where a finite k-constraint is realized through an extra coding shell on top of a Finite-State Machine with a basic 2-to-3 mapping of the code. 
   
   
       24 . A method as claimed in  claim 5 , where d=2 and r=2, and T max  equals 10. 
   
   
       25 . A method as claimed in  claim 24 , where T=T max =10 and where the number of sub-codes S equals 4. 
   
   
       26 . A method as claimed in  claim 25 , where a one of the sub-codes has a mapping with m=8 and n=14 and the other sub-codes have a mapping with m=8 and n=15. 
   
   
       27 . A method as claimed in  claim 24 , where for each sub-code trailing bits are specified for the different code word types by the following set of rules, that is,
 the n-bit code words of the 1st type end with   “000”,   the n-bit code words of the 2nd type end with   “000100”,   the n-bit code words of the 3rd type end with   “000100100”,   the n-bit code words of the 4th type end with   “0001001001001”,   the n-bit code words of the 5th type end with   “00010”,   the n-bit code words of the 6th type end with   “00010010”,   the n-bit code words of the 7th type end with   “00010010010”,   the n-bit code words of the 8th type end with   “0001”,   the n-bit code words of the 9th type end with   “0001001”,   the n-bit code words of the 10th type end with   “0001001001”,   and where leading bits of the code words belonging to the different coding classes are determined by the following set of rules, that is,   the n-bit code words of a coding state of the 1st class start with   “000”,   the n-bit code words of a coding state of the 2nd class start with   “000” or “001000”,   the n-bit code words of a coding state of the 3rd class start with   “000”, “001000” or “001001000”,   the n-bit code words of a coding state of the 4th class start with   “000”, “001000”, “001001000” or “001001001000”,   the n-bit code words of a coding state of the 5th class start with   “000”, “001000”, “001001000”, “001001001000” or “01000”,   the n-bit code words of a coding state of the 6th class start with   “000”, “00000”, “001001000”, “001001001000”, “01000” or “01001000”,   the n-bit code words of a coding state of the 7th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000” or “01001001000”,   the n-bit code words of a coding state of the 8th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000” or “1000”,   the n-bit code words of a coding state of the 9th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000”, “1000” or “1001000”,   the n-bit code words of a coding state of the 10th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000”, “1000”, “1001000” or “1001001000”.   
   
   
       28 . A method as claimed in  claim 26 , where for the first sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the T=10 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =12, p 4 =12, p 5 =16, p 6 =17, p 7 =18, p 8 =24, p 9 =26 and p 10 =26, and where for the second sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =11, p 5 =15, p 6 =16, p 7 =16, p 8 =21, p 9 =23 and p 10 =24, and where for the third sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =7, p 2 =9, p 3 =10, p 4 =10, p 5 =13, p 6 =14, p 7 =15, p 8 =19, p 9 =21 and p 10 =22, and where for the fourth sub-code the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =6, p 2 =8, p 3 =9, p 4 =9, p 5 =12, p 6 =13, p 7 =13, p 8 =18, p 9 =19 and p 10 =20. 
   
   
       29 . A method as claimed in  claim 14 , where the number of non-trivial coding classes T equals 7, and where the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 non-trivial coding classes of coding states amounts to p 1 =4, p 2 =5, p 3 =6, p 4 =6, p 5 =9, p 6 =10 and p 7 =10. 
   
   
       30 . A method as claimed in  claim 29 , where a k=12 constraint is realized through an extra coding state in the finite-state-machine of the code. 
   
   
       31 . A method as claimed in  claim 29 , where a method of guided scrambling is used for DC-control. 
   
   
       32 . A coder for of converting a user bitstream into a coded bitstream by means of an overall channel code by converting M-bit information words into N-bit code words, the coder comprising sub-coders repeated in a cyclical order with a predetermined repeat period, each sub-coder using a sub-code, wherein each sub-coder is arranged to receive m-bit information words, where m i  is an integer characteristic for each of the sub-codes, and is arranged to convert the received m i -bit information words into n i -bit code words, where n i  is an integer characteristic for each of the sub-codes, and where for each sub-code, said characteristic integer number n i  is greater than said characteristic integer number m i , such that the sum of the m i -numbers of all sub-codes within said repeat period equals M, and that the sum of the n i -numbers of all sub-codes within said repeat period equals N, where for each sub-code, its n i -bit code words are logically or physically divided into a number of T max  different code-word types and logically or physically arranging its n i -bit code words into T max  coding classes of coding states such that, for a given sub-code, an n i -bit code word of type t, where t is an integer number between 1 and T max , can be concatenated into a concatenated set of code words thus generating said coded bitstream and realizing said N-bit code-words of said overall channel code, with an n i+1 -bit code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index T max +1−t. 
   
   
       33 . A coder as claimed in  claim 32 , where the code-word type is determined by a number of trailing bits of said code-word. 
   
   
       34 . A coder as claimed in  claim 32 , where the code-word type is determined by all bits of said code-word, together with at least one bit of a preceding code-word. 
   
   
       35 . A coder claimed in  claim 33 , wherein the concatenated set of N-bit code words realizing said coded bitstream satisfy a dkr-constraint, where d refers to a minimum number of zero-bits between two consecutive one-bits in the coded bitstream, and k refers to a maximum number of zero-bits between two consecutive one-bits in the coded bitstream, and where r indicates a maximum number of consecutive minimum runs of d zero-bits each preceded by a one-bit. 
   
   
       36 . A coder as claimed in  claim 35 , where the number of different code-word types  T  and non-empty coding classes, wherein a non-empty coding class is defined to have at least one coding state, is not larger than T max =1+(d+1)×(r+1). 
   
   
       37 . A coder as claimed in  claim 35 , where the number of different code-word types T and the number of different non-empty coding classes T, where T equals T max =1+(d+1)×(r+1). 
   
   
       38 . A coder as claimed in  claim 36 , where d=1 and r=2, and T max  equals 7. 
   
   
       39 . A coder as claimed in  claim 38 , where T=T max =7 and where the number of sub-coders S equals 6. 
   
   
       40 . A coder as claimed in  claim 39 , where one of the sub-coders uses a mapping with m=8 and n=11, and the other sub-coders use a mapping with m=8 and n=12. 
   
   
       41 . A coder as claimed in  claim 40 , where T=T max =7 and where the number of sub-coders S equals 3. 
   
   
       42 . A coder as claimed in  claim 41 , where one of the sub-coders uses m=9 and n=14, and the other sub-coders use m=9 and n=13. 
   
   
       43 . A coder as claimed in  claim 38 , where T=T max =7 and where the number of sub-coders S equals 1. 
   
   
       44 . A coder as claimed in  claim 43 , where the sub-coder uses a mapping with m=4 and n=6. 
   
   
       45 . A coder as claimed in  claim 43 , where the single sub-coder uses a mapping with m=2 and n=3. 
   
   
       46 . A coder as claimed in  claim 36 , where, for each of the sub-coders, each of said T≦T max  non-empty coding classes of coding states comprises p 1 , p 2 , . . . , p max  coding states, wherein the trivial empty coding classes are omitted, such that for the numbers representing the non-zero number of states of the non-empty coding classes p 1 ≦p 2 ≦ . . . ≦p max , and with p max  giving the total number of coding states for said considered sub-coder, further characterized in that each of the p i  coding states of a given considered class “i”, is also a coding state of all classes that have an index larger than “i”. 
   
   
       47 . A coder as claimed in  claim 38 , where for each sub-coder trailing bits are specified for the different code word types by the following set of rules, that is,
 the n-bit code words of the 1st type end with   “00”,   the n-bit code words of the 2nd type end with   “0010”,   the n-bit code words of the 3rd type end with   “001010”,   the n-bit code words of the 4th type end with   “00101010”,   the n-bit code words of the 5th type end with   “001”,   the n-bit code words of the 6th type end with   “00101”,   the n-bit code words of the 7th type end with   “0010101”,   and where leading bits of the code words belonging to the different coding classes are determined by the following set of rules, that is,   the n-bit code words of a coding state of the 1st class start with   “00”,   the n-bit code words of a coding state of the 2nd class start with   “00” or “0100”,   the n-bit code words of a coding state of the 3rd class start with   “00”, “0100” or “010100”,   the n-bit code words of a coding state of the 4th class start with   “00”, “0100”, “010100” or “01010100”,   the n-bit code words of a coding state of the 5th class start with   “00”, “0100”, “010100”, “01010100” or “100”,   the n-bit code words of a coding state of the 6th class start with   “00”, “0100”, “010100”, “01010100”, “100” or “10100”,   the n-bit code words of a coding state of the 7th class start with   “00”, “0100”, “010100”, “01010100”, “100”, “10100” or “1010100”.   
   
   
       48 . A coder as claimed in  claim 40 , where for the first sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =11, p 2 =15, p 3 =17, p 4 =17, p 5 =24, p 6 =27 and p 7 =28, and where for the second sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =10, p 2 =14, p 3 =15, p 4 =16, p 5 =22, p 6 =25 and p 7 =26, and where for the third sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =9, p 2 =13, p 3 =14, p 4 =14, p 5 =20, p 6 =23 and p 7 =24 and where for the fourth sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =13, p 4 =13, p 5 =19, p 6 =21 and p 7 =22 and where for the fifth sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =12, p 4 =12, p 5 =17, p 6 =19 and p 7 =20 and where for the sixth sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =12, p 5 =16, p 6 =18 and p 7 =19. 
   
   
       49 . A coder as claimed in  claim 42 , where for the first sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =11, p 5 =16, p 6 =18 and p 7 =19, and where for the second sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =8, p 2 =12, p 3 =13, p 4 =13, p 5 =19, p 6 =21 and p 5 =22, and where for the third sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 classes of coding states amounts to p 1 =10, p 2 =14, p 3 =15, p 4 =16, p 5 =22, p 6 =25 and p 7 =26. 
   
   
       50 . A coder as claimed in  claim 44  , where the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the T=7 classes of coding states amounts to p 1 =3, p 2 =4, p 3 =5, p 4 =5, p 5 =7, p 6 =8 and p 7 =8. 
   
   
       51 . A coder as claimed in  claim 50 , where a finite k-constraint is realized through an extra coding state. 
   
   
       52 . A coder as claimed in  claim 45 , where a number of non-trivial coding classes T equals 6, with coding class number 4 being the empty one, yielding p 4 =0, and where the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the non-trivial coding classes T of coding states amounts to p 1 =2, p 2 =2, p 3 =3, p 5 =4, p 6 =5 and p 7 =5. 
   
   
       53 . A coder as claimed in  claim 52 , where a parity-preserve property is realized through at least one extra coding state. 
   
   
       54 . A coder as claimed in  claim 52 , where the sub-coder comprises a Finite-State Machine with a basic 2-to-3 mapping of the code and where a finite k-constraint is realized through an extra coding shell on top of the Finite-State Machine. 
   
   
       55 . A coder as claimed in  claim 36 , where d=2 and r=2, and T max  equals 10. 
   
   
       56 . A coder as claimed in  claim 55 , where T=T max =10 and where the number of sub-coders S equals 4. 
   
   
       57 . A coder as claimed in  claim 56 , where a one of the sub-coders uses a mapping with m=8 and n=14 and the other sub-coders use a mapping with m=8 and n=15. 
   
   
       58 . A coder as claimed in  claim 55 , where for each sub-coder trailing bits are specified for the different code word types by the following set of rules, that is,
 the n-bit code words of the 1st type end with   “000”,   the n-bit code words of the 2nd type end with   “000100”,   the n-bit code words of the 3rd type end with   “000100100”,   the n-bit code words of the 4th type end with   “000100100100”,   the n-bit code words of the 5th type end with   “00010”,   the n-bit code words of the 6th type end with   “00010010”,   the n-bit code words of the 7th type end with “00010010010”,   the n-bit code words of the 8th type end with   “0001”,   the n-bit code words of the 9th type end with   “0001001”,   the n-bit code words of the 10th type end with   “0001001001”,   and where leading bits of the code words belonging to the different coding classes are determined by the following set of rules, that is,   the n-bit code words of a coding state of the 1st class start with   “000”,   the n-bit code words of a coding state of the 2nd class start with   “000” or “001000”,   the n-bit code words of a coding state of the 3rd class start with   “000”, “001000” or “001001000”,   the n-bit code words of a coding state of the 4th class start with   “000”, “001000”, “001001000” or “001001001000”,   the n-bit code words of a coding state of the 5th class start with   “000”, “001000”, “001001000”, “001001001000” or “01000”,   the n-bit code words of a coding state of the 6th class start with   “000”, “00000”, “001001000”, “001001001000”, “01000” or “01001000”,   the n-bit code words of a coding state of the 7th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000” or “01001001000”,   the n-bit code words of a coding state of the 8th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000” or “1000”,   the n-bit code words of a coding state of the 9th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000”, “1000” or “1001000”,   the n-bit code words of a coding state of the 10th class start with   “000”, “001000”, “001001000”, “001001001000”, “01000”, “01001000”, “01001001000”, “1000”, “1001000” or “1001001000”.   
   
   
       59 . A coder as claimed in  claim 32 , where for the first sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the T=10 classes of coding states amounts to p 1 =8, p 2 =11, p 3 =12, p 4 =12, p 5 =16, p 6 =17, p 7 =18, p 8 =24, p 9 =26 and p 10 =26, and where for the second sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =7, p 2 =10, p 3 =11, p 4 =11, p 5 =15, p 6 =16, p 7 =16, p 8 =21, p 9 =23 and p 10 =24, and where for the third sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =7, p 2 =9, p 3 =10, p 4 =10, p 5 =13, p 6 =14, p 7 =15, p 8 =19, p 9 =21 and p 10 =22, and where for the fourth sub-coder the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 , p 8 , p 9 , p 10  of coding states for each of the 10 classes of coding states amounts to p 1 =6, p 2 =8, p 3 =9, p 4 =9, p 5 =12, p 6 =13, p 7 =13, p 8 =18, p 9 =19 and p 10 =20. 
   
   
       60 . A coder as claimed in  claim 45 , where the number of non-trivial coding classes T equals 7, and where the number p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7  of coding states for each of the 7 non-trivial coding classes of coding states amounts to p 1 =4, p 2 =5, p 3 =6, p 4 =6, p 5 =9, p 6 =10 and p 7 =10. 
   
   
       61 . A coder as claimed in  claim 60 , where a k=12 constraint is realized through an extra coding state in the finite-state-machine of the sub coder. 
   
   
       62 . A coder as claimed in  claim 60 , where a method of guided scrambling is used for DC-control. 
   
   
       63 . A record carrier comprising a signal comprising a coded bit stream that is coded using a method as claimed in  claim 1 . 
   
   
       64 . Recorder comprising a coder as claimed in  claim 32 .