Integration Scheme for Dual Work Function Metal Gates

Abstract

A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants Lanthanide series dopants into a gate polysilicon layer of NMOS.

1 - 49 . (canceled) 
   
   
       50 . An NMOS transistor, comprising:
 a semiconductor substrate;   a gate dielectric coupled to said semiconductor substrate;   a fully silicided gate electrode coupled to said gate dielectric; and   source/drain regions located within said semiconductor substrate;   wherein said fully silicided gate electrode of said NMOS transistor includes a lanthanide series dopant.   
   
   
       51 . The NMOS transistor of  claim 50  wherein said fully silicided gate electrode also include an As dopant. 
   
   
       52 . The NMOS transistor of  claim 50  wherein said lanthanide series dopant is Yb. 
   
   
       53 . The NMOS transistor of  claim 50  wherein said gate dielectric includes a lanthanide series dopant. 
   
   
       54 . The NMOS transistor of  claim 53  wherein said lanthanide series dopant is Yb. 
   
   
       55 . A PMOS transistor, comprising:
 a semiconductor substrate;   a gate dielectric coupled to said semiconductor substrate;   a fully silicided gate electrode coupled to said gate dielectric;   source/drain regions located within said semiconductor substrate;   wherein said fully silicided gate electrode of said PMOS transistor includes a Group IIIa dopant.   
   
   
       56 . The PMOS transistor of  claim 55  wherein said fully silicided gate electrode also includes oxygen. 
   
   
       57 . The PMOS transistor of  claim 55  wherein said Group IIIa dopant is Ga. 
   
   
       58 . The PMOS transistor of  claim 55  wherein said gate dielectric includes a Group IIIa dopant. 
   
   
       59 . The PMOS transistor of  claim 58  wherein said Group IIIa dopant is Ga.