mosfet for high voltage applications and a method of fabricating same

Abstract

A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material. P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to be lifted significantly above the substrate voltage without the occurrence of excessive leakage currents.

1 . A Metal-Oxide-Semiconductor device comprising
 a semiconductor-on-insulator substrate having a layer of insulating material over which is provided   a doped semiconductor region of a first conductivity type,   a gate region of said first conductivity type,   a source region and drain region being provided at a surface of said device within said region of said first conductivity type, said source and drain regions including respective doped semiconductor regions of a second conductivity type and defining a channel therebetween,   wherein a gap is provided between said source and drain regions and said layer of insulating material, the device further comprising a plug region of said second conductivity type extending from said surface of said device at or adjacent said source region into said doped semiconductor region of said first conductivity type and being electrically shorted to said source region.   
     
     
         2 . A device according to  claim 1 , wherein said plug region extends from said surface of said device to said layer of insulating material. 
     
     
         3 . A device according to  claim 1 , comprising a PMOS transistor, wherein said first conductivity type is n-type and said second conductivity type is p-type. 
     
     
         4 . A device according to  claim 1 , comprising an NMOS transistor, wherein said first conductivity type is p-type and said second conductivity type is n-type. 
     
     
         5 . A device according to  claim 1 , wherein said plug region at least partially overlaps said source region. 
     
     
         6 . A device according to  claim 1 , wherein said plug region is electrically shorted to said source region by means of a conductive contact. 
     
     
         7 . A method of fabricating a Metal-Oxide-Semiconductor device, the method comprising
 providing a semiconductor-on-insulator substrate having a layer of insulating material over which is provided a doped semiconductor region of a first conductivity type,   providing a gate region of said first conductivity type,   providing by diffusion a source region and drain region at a surface of said device within said region of said first conductivity type, said source and drain regions including respective doped semiconductor regions of a second conductivity type and defining a channel therebetween,   wherein a gap is provided between said source and drain regions and said layer of insulating material, the method further comprising forming a plug region of said second conductivity type which extends from said surface of said device at or adjacent said source region into said doped semiconductor region of said first conductivity type and being electrically shorted to said source region.   
     
     
         8 . An integrated circuit including a MOS device according to  claim 1 .