Solid state memory (ssm), computer system including an ssm, and method of operating an ssm

Abstract

In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.

1 . A method of storing data in a solid state memory including first and second memory layers, said method comprising:
 executing a first assessment of whether received data is hot data or cold data;   storing received data which is assessed as hot data during the first assessment in the first memory layer;   storing received data which is assessed as cold data during the first assessment in the second memory layer;   executing a second assessment of whether the data stored in the first memory layer is hot data or cold data; and   migrating data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.   
     
     
         2 . The method as claimed in  claim 1 , wherein an operational speed of the first memory layer is higher than an operational speed of the second memory layer. 
     
     
         3 . The method as claimed in  claim 2 , wherein the first and second memory layers are comprised of respectively different types of memory cells. 
     
     
         4 . The method as claimed in  claim 1 , wherein the first memory layer is comprised of single-level flash memory cells and the second memory layer is comprised of multi-level flash memory cells. 
     
     
         5 . The method as claimed in  claim 1 , wherein the first and second memory layers are comprised of multi-level flash memory cells, and wherein data is stored in a least-significant bit only of the multi-level flash memory cells of the first memory layer. 
     
     
         6 . The method as claimed in  claim 1 , wherein the first and second memory layers are comprised of a same type of memory cell. 
     
     
         7 . The method as claimed in  claim 6 , wherein a mapping grain of the first memory layer is finer than a mapping grain of the second memory layer. 
     
     
         8 . The method as claimed in  claim 7 , wherein the first and second memory layers are comprised of single-level flash memory cells. 
     
     
         9 . The method as claimed in  claim 7 , wherein the first and second memory layers are comprised of multi-level flash memory cells. 
     
     
         10 . The method as claimed in  claim 1 , wherein the data which is first assessed as cold data during the first assessment is temporarily stored in the first memory layer prior to being stored in the second memory layer. 
     
     
         11 . The method as claimed in  claim 1 , wherein the second assessment further includes a determination of whether unused memory capacity of the first memory layer is less than a threshold. 
     
     
         12 . The method as claimed in  claim 1 , wherein the second assessment is executed a periodic intervals or when the solid state memory enters an idle state. 
     
     
         13 . The method as claimed in  claim 1 , wherein the first and second memory layers are contained in a solid state drive. 
     
     
         14 . The method as claimed in  claim 1 , wherein the first and second memory layers are contained in the main memory of a computer system. 
     
     
         15 . A method of storing received data in a solid state memory comprising initially storing hot data in a high-speed memory layer and, and then migrating a portion of the data stored in the high-speed memory layer to a low-speed memory layer for storing cold data. 
     
     
         16 . The method as claimed in  claim 15 , wherein the high-speed and low-speed non-volatile memory layers are comprised of respectively different types of memory cells. 
     
     
         17 . The method as claimed in  claim 15 , wherein the high-speed and low-speed non-volatile memory layers are comprised of a same type of memory cells. 
     
     
         18 . A solid state memory system, comprising:
 a first memory layer;   a second memory layer; and   a memory controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the first memory layer, and to store received data which is assessed as cold data during the first assessment in the second memory layer,   wherein the memory controller is further configured to execute a second assessment of whether the data stored in the first memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.   
     
     
         19 . The solid state memory as claimed in  claim 18 , wherein the memory controller is operatively connected to the first and second memory layers using respectively different data channels. 
     
     
         20 . The solid state memory as claimed in  claim 18 , wherein the memory controller is operatively connected to the first and second memory layers using common data channels. 
     
     
         21 . The solid state memory as claimed in  claim 18 , wherein an operational speed of the first memory layer is higher than an operational speed of the second memory layer. 
     
     
         22 . The solid state memory as claimed in  claim 21 , wherein the first and second memory layers are comprised of respectively different types of memory cells. 
     
     
         23 . The solid state memory as claimed in  claim 21 , wherein the first and second memory layers are comprised of a same type of memory cells. 
     
     
         24 . The solid state memory as claimed in  claim 18 , wherein the data which is first assessed as cold data during the first assessment is temporarily stored in the first memory layer prior to being stored in the second memory layer. 
     
     
         25 . The solid state memory as claimed in  claim 18 , wherein the first and second memory layers are contained in a solid state drive. 
     
     
         26 . The solid state memory as claimed in  claim 18 , wherein the first and second memory layers are contained in the main memory of a computer system. 
     
     
         27 . A solid state memory system which is configured to operatively connect to a computer operating system and which comprises first and second memory layers, wherein an operational speed of the first memory layer is greater than an operational speed of the second memory layer, and wherein the first memory area is operationally hidden from the computer operating system when the solid state memory is operatively connected to the computer operating system. 
     
     
         28 . The solid state memory system of  claim 27 , wherein the solid state memory further comprises a controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the first memory layer, and to store received data which is assessed as cold data during the first assessment in the second memory layer,
 wherein the memory controller is further configured to execute a second assessment of whether the data stored in the first memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.   
     
     
         29 . A computer system comprising a processor and a solid state memory, wherein the solid state memory comprises a high-speed memory layer and a low-speed memory layer, and wherein the high-speed memory area is operationally hidden from the processor. 
     
     
         30 . The computer system as claimed in  claim 29 , wherein the solid state memory further comprises a memory controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the high-speed memory layer, and to store received data which is assessed as cold data during the first assessment in the low-speed memory layer,
 wherein the memory controller is further configured to execute a second assessment of whether the data stored in the high-speed memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the high-speed memory layer to the low-speed memory layer.   
     
     
         31 . The computer system as claimed in  claim 29 , wherein the memory is a solid state drive. 
     
     
         32 . The computer system as claimed in  claim 29 , wherein the memory is a main memory.