Data processor

Abstract

It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.

1 - 9 . (canceled) 
     
     
         10 . A data processor comprising:
 a clock pulse generation circuit; and   a circuit module operating on a clock signal output from said clock pulse generation circuit;   wherein said clock pulse generation circuit stepwise changes frequencies of said clock signal from low to high frequencies, when a power-on reset is released according to input of a reset signal to said data processor from outside,   wherein said clock pulse generation circuit comprises a PLL circuit and a divider which is operated to effect said stepwise changes of frequencies, and   wherein said circuit module includes a central processing unit, an asynchronous DRAM controller, a display controller, and a rendering controller.   
     
     
         11 . The data processor according to  claim 10 ,
 wherein, upon changing from a power to a power-down or standby state, said divider is operated so as to change the frequency of said clock signal from high frequency to low frequency in a stepwise manner.   
     
     
         12 . The data processor according to  claim 10 , wherein, upon entry to a standby state, said clock pulse generation circuit changes the frequency of said clock signal from high frequency to low frequency in a stepwise manner. 
     
     
         13 . The data processor according to  claim 10 ,
 wherein said clock pulse generation circuit changes the frequency of said clock signal from high frequency to low frequency in response to a standby signal, and   wherein when said clock signal has reached a predetermined low frequency, said clock pulse generation circuit stops supplying clock signals to said circuit module.   
     
     
         14 . The data processor according to  claim 10 ,
 wherein said clock pulse generation circuit changes the frequency of said clock signal from high frequency to low frequency according to a power-down signal, and then executes a power-down state.