Semiconductor memory device

Abstract

A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller.

1 . A semiconductor memory device, comprising:
 a memory array having a plurality of memory cells arranged in matrix;   first and second ports independent of each other, performing transmission and reception of an input/output signal; and   a selection circuit capable of selection in accordance with addresses input to said first and second ports respectively, with periods of access to said memory array overlapping with each other;   said memory array including   a plurality of first and second word lines provided in correspondence with memory cell rows respectively, and   a plurality of first and second bit lines provided in correspondence with memory cell columns respectively,   each said memory cell including   a flip-flop circuit for setting first and second storage nodes to one and another of first and second potential levels in accordance with stored data,   a first gate transistor having a gate electrically coupled to a corresponding first word line, for electrically coupling a corresponding first bit line to said flip-flop circuit, and   a second gate transistor having a gate electrically coupled to a corresponding second word line, for electrically coupling a corresponding second bit line to said flip-flop circuit,   said memory array further including a plurality of power supply lines provided in correspondence with the memory cell rows respectively, each for supplying an operation voltage of the flip-flop circuit in the memory cell in a corresponding memory cell row,   said selection circuit including   first and second row decoders provided in correspondence with said first and second ports and outputting row selection instructions in accordance with input addresses, respectively, and   a plurality of word drivers provided in correspondence with the memory cell rows respectively, each for driving the corresponding first and second word lines in accordance with a result of row selection by said first and second row decoders,   each said word driver setting a voltage level of a corresponding word line to a prescribed voltage level when it receives an input of the row selection instruction from at least one of said first and second row decoders, and   in each said memory cell row, said corresponding power supply line being formed in an identical metal interconnection layer where the word line is formed, and being provided adjacent to and between said corresponding first word line and said corresponding second word line.   
   
   
       2 . A semiconductor memory device, comprising:
 N memory blocks arranged along a column direction, and each having a plurality of memory cells arranged in matrix;   N first and second ports independent of each other, provided in correspondence with said memory blocks, and each performing transmission and reception of an input/output signal;   N selection circuits each capable of selection in accordance with addresses input to the first and second ports corresponding to said memory block respectively, with periods of access to corresponding memory block overlapping with each other;   each said memory block including   a plurality of first and second word lines provided in correspondence with memory cell rows respectively,   a plurality of first bit lines connected to corresponding said first port and provided in correspondence with memory cell columns respectively, and   a plurality of second bit lines connected to corresponding said second port and provided in correspondence with the memory cell columns respectively,   each said memory cell including   a flip-flop circuit for setting first and second storage nodes to one and another of first and second potential levels in accordance with stored data,   a first gate transistor having a gate electrically coupled to a corresponding first word line, for electrically coupling a corresponding first bit line to said flip-flop circuit, and   a second gate transistor having a gate electrically coupled to a corresponding second word line, for electrically coupling a corresponding second bit line to said flip-flop circuit,   each said selection circuit including   first and second row decoders provided in correspondence with said first and second ports and outputting row selection instructions in accordance with input addresses, respectively, and   a plurality of word drivers provided in correspondence with the memory cell rows respectively, each for driving the corresponding first and second word lines in accordance with a result of row selection by said first and second row decoders; and   (N+1) reading and writing circuits each electrically coupled to at least one of one and another of said plurality of first and second bit lines provided in correspondence with said first and second ports of adjacent memory blocks, for performing data reading and data writing, one reading and writing circuit being provided in correspondence with said first port on one side of said memory block and one reading and writing circuit being provided in correspondence with said second port on another side thereof; wherein   when an identical memory block is selected and said first and second ports are used to perform data reading, the reading and writing circuit on one side of said identical memory block is used and connected to said plurality of first bit lines to perform data reading through said first port and the reading and writing circuit on another side is used and connected to said plurality of second bit lines to perform data reading through said second port, and   when two memory blocks on one side and another side are selected and said first and second ports are used to perform data reading, the reading and writing circuit on one side provided in correspondence with the memory block on one side out of said two memory blocks is used and connected to said plurality of first bit lines to perform data reading through said first port and the reading and writing circuit on another side provided in correspondence with the memory block on another side out of said two memory blocks is used and connected to said plurality of second bit lines to perform data reading through said second port.   
   
   
       3 . A semiconductor memory device, comprising:
 a memory array having a plurality of memory cells arranged in matrix;   first and second ports independent of each other, performing transmission and reception of an input/output signal;   a selection circuit capable of selection in accordance with addresses correspondingly input to said first and second ports, with periods of access to said memory array overlapping with each other;   said memory array-including   a plurality of first and second word lines provided in correspondence with memory cell rows respectively, and   a plurality of first and second bit lines provided in correspondence with memory cell columns respectively,   each said memory cell including   a flip-flop circuit for setting first and second storage nodes to one and another of first and second potential levels in accordance with stored data,   a first gate transistor having a gate electrically coupled to a corresponding first word line, for electrically coupling a corresponding first bit line to said flip-flop circuit, and   a second gate transistor having a gate electrically coupled to a corresponding second word line, for electrically coupling a corresponding second bit line to said flip-flop circuit,   said selection circuit including   first and second row decoders provided in correspondence with said first and second ports and outputting row selection instructions in accordance with input addresses, respectively, and   a plurality of word drivers provided in correspondence with the memory cell rows respectively, each for driving the corresponding first and second word lines in accordance with a result of row selection by said first and second row decoders;   a first reading and writing circuit provided in correspondence with said first port and electrically coupled to said plurality of first bit lines, for performing data reading and data writing;   a second reading and writing circuit provided in correspondence with said second port and electrically coupled to said plurality of second bit lines, for performing data reading and data writing; and   a plurality of switching circuits corresponding to said first reading and writing circuit, provided in correspondence with the memory cell columns respectively, and each switching connection with the first bit line to electrical connection with the second bit line in response to an instruction.   
   
   
       4 . The semiconductor memory device according to  claim 3 , wherein
 said plurality of memory cells included in said memory array are arranged along the row in a prescribed unit,   a memory cell group in said prescribed unit stores external data in a prescribed unit continuously from a lower address row toward an upper address row,   said semiconductor memory device further comprises a control circuit controlling said plurality of switching circuits,   at least one of said first and second row decoders of said selection circuit outputs a row selection instruction for accessing the memory cell group in a prescribed unit selected in accordance with said input address during data reading,   at least one of said first and second word lines corresponding to the lower address row and the upper address row adjacent to each other is activated in accordance with the row selection instruction from at least one of said first and second row decoders, and   when the first and the second word lines corresponding to said lower address row and said upper address row adjacent to each other are both activated, among said plurality of switching circuits, said control circuit gives a switching instruction to the switching circuit corresponding to the memory cell column in the upper address row in said selected memory cell group in the prescribed unit in accordance with said input address.   
   
   
       5 . The semiconductor memory device according to  claim 4 , wherein
 said input address has a row address and a column address designating a row and a column respectively for accessing a memory cell group in a prescribed unit,   when the row address and the column address included in said input address select a starting memory cell arranged in said prescribed unit, said first row decoder of said selection circuit outputs a row selection instruction activating said first word line based on said row address, and   when the row address and the column address included in said input address select a memory cell other than the starting memory cell arranged in said prescribed unit, based on the row address included in said input address, said first row decoder of said selection circuit outputs a row selection instruction activating said first word line corresponding to the lower address row and said second row decoder of said selection circuit outputs a row selection instruction activating the second word line corresponding to the higher address row.   
   
   
       6 . The semiconductor memory device according to  claim 3 , further comprising a sorting circuit provided in correspondence with said first reading and writing circuit and changing sequence of data bits output from said first reading and writing circuit in accordance with said input address. 
   
   
       7 . A semiconductor memory device, comprising:
 a memory array having a plurality of memory cells arranged in matrix;   first and second ports independent of each other, performing transmission and reception of an input/output signal;   a selection circuit capable of selection in accordance with addresses correspondingly input to said first and second ports, with periods of access to said memory array overlapping with each other;   said memory array including   a plurality of first and second word lines provided in correspondence with memory cell rows respectively, and   a plurality of first and second bit lines provided in correspondence with memory cell columns respectively,   each said memory cell including   a flip-flop circuit for setting first and second storage nodes to one and another of first and second potential levels in accordance with stored data,   a first gate transistor having a gate electrically coupled to a corresponding first word line, for electrically coupling a corresponding first bit line to said flip-flop circuit, and   a second gate transistor having a gate electrically coupled to a corresponding second word line, for electrically coupling a corresponding second bit line to said flip-flop circuit,   said selection circuit including   a row decoder outputting a row selection instruction in accordance with an input address, and   a plurality of word driver units provided in correspondence with the first and second word lines corresponding to two adjacent memory cell rows, each for driving the corresponding first and second word lines based on a result of row selection; and   first and second reading and writing circuits provided in correspondence with said first and second ports respectively and electrically coupled to said plurality of first and second bit lines respectively, for performing data reading and data writing.   
   
   
       8 . The semiconductor memory device according to  claim 7 , wherein
 each said word driver unit drives only any one of the corresponding first and second word lines in response to a control instruction.   
   
   
       9 . The semiconductor memory device according to  claim 8 , further comprising an address determination circuit outputting said control instruction based on a column address included in said input address.