US2009056118A1PendingUtilityA1

Method of manufacturing a combined multilayer circuit board having embedded chips

Assignee: CHANG ROGERPriority: Aug 29, 2006Filed: Oct 31, 2008Published: Mar 5, 2009
Est. expiryAug 29, 2026(~0.1 yrs left)· nominal 20-yr term from priority
Inventors:Roger Chang
Y10T29/49128Y10T29/49165H05K 3/4652H05K 3/28Y10T29/49126Y10T29/49155H05K 2203/068Y10T29/4913Y10T29/49146H05K 1/186H05K 2201/0358H05K 2201/10674H05K 2201/09536H05K 2203/085H05K 2203/063H05K 1/187H05K 3/4623H10W 90/754H10W 90/724H10W 72/884H10W 72/0198H10W 70/685H10W 70/682H10W 90/00H10W 70/614H10W 70/095H10W 70/05
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a combined multilayer circuit board having embedded chips comprising acts of:
 (a) providing at least two multilayer circuit boards, wherein at least one of the multilayer circuit boards is fabricated by steps of
 (a1) preparing a single-layer FR4 printed circuit board having multiple chip sections arranged in matrix, and each chip section having
 a FR4 substrate; 
 multiple conducting wires formed on the FR4 substrate of each chip section; 
 an insulating coating coated on a portion of the multiple conducting wires; and 
 multiple contacts defined as the exposed portion of the multiple conducting wires; 
 
 (a2) attaching at least one chip to the corresponding chip section of the single-layer FR4 printed circuit board, wherein each chip is electronically connected to the contacts on the corresponding single-layer FR4 printed circuit board; 
 (a3) attaching a frame to the single-layer FR4 printed circuit board, wherein the frame has multiple enclosures corresponding to the chip sections on the single-layer FR4 printed circuit board to enclose the corresponding chip section and the corresponding chip; 
 (a4) attaching a semi-fluid glue sheet to the frame to cover the frame; 
 (a5) vacuum pressing a conductive layer on the semi-fluid glue sheet to fill inside of the enclosures with glue of the semi-fluid glue sheet to encapsulate the chips; and 
 (a6) forming multiple inner conductive vias by drilling multiple holes through the multilayer circuit board and then electroplating peripheries defining the holes to electronically connect the conducting wires to the conductive layer in the multilayer circuit board; and 
   at least one of the other multilayer circuit boards is fabricated by steps of   (b) combining the at least two multilayer circuit boards to form a combined multilayer circuit board, wherein the act (b) comprises steps of
 (b1) reversing one of the multilayer circuit boards; and 
 (b2) vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board with multiple glue layers, and each glue layer sandwiched in between the two multilayer circuit boards; 
   (c) forming multiple outer conductive vias by drilling multiple through holes through the combined multilayer circuit board and then electroplating peripheries defining the through holes to electronically interconnect the conducting wires and the conductive layers in the at least two multilayer circuit boards; and   (d) forming circuits and contacts on the combined multilayer circuit board by etching patterns on the conductive layers and coating an insulating lacquer layer on a portion of the patterned conductive layers.

Join the waitlist — get patent alerts

Track US2009056118A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.