US2009058501A1PendingUtilityA1

Semiconductor device

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Assignee: WATANABE HIROSHIPriority: Sep 28, 2004Filed: Oct 31, 2008Published: Mar 5, 2009
Est. expirySep 28, 2024(expired)· nominal 20-yr term from priority
H10D 30/683G11C 13/0004H10B 69/00
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Claims

Abstract

A semiconductor device includes an input terminal, a first aging device whose source is connected to the input terminal to turn on at τ 1 and turn off at τ 2 (>τ 1 ), a second aging device whose source is connected to the input terminal, whose gate is connected to the drain of the first aging device, and whose drain is connected to the gate of the first aging device to turn on at τ 3 and turn off at τ 4 (>τ 3 ), a first switch whose one terminal is connected to the drain of the first aging device to turn off when the second aging device is on, a second switch whose one terminal is connected to the drain of the second aging device to turn off when the first aging device is on, and an output terminal connected to the other terminals of the first and second switch elements.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a first terminal;   a second terminal; and   an aging device comprising a source, a drain, and a gate, conduction being made between the source and the drain after elapse of a predetermined time after electric charges are injected into the gate, which is referred to as a normally-on type, the source being connected to the first terminal, the drain being connected to the second terminal, the gate being connected to the drain.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a booster or a regulator inserted between the gate and the drain. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the aging device has a double-layer gate configuration, which comprises a floating gate and a control gate, and the predetermined life is defined by a time elapsed after injection of an electric charge into the floating gate until an on and off change of the aging device is detected. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising:
 at least one of a first function block and a second function block connected to the output terminal; and   a third function block connected to the input terminal, the third function block including a power supply.   
     
     
         5 . A semiconductor system comprising:
 N semiconductor devices each comprising the semiconductor device according to  claim 1 ;   a first function block and a second function block connected to an output terminal of a first semiconductor device among the N semiconductor devices; and   an i+2-th function block connected to an input terminal of an i-th semiconductor device among the N semiconductor devices, i being a natural number from 2 to N,   an output terminal of the i-th semiconductor device being connected to an input terminal of the i−1-th semiconductor device.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein
 the aging device includes a plurality of aging device cells of the normally-on type, which are connected in series to form a plurality of rows, the plurality of rows are further connected in parallel with one another.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein each of the rows includes a trimming circuit connected in series, the trimming circuit comprising a MOS transistor and an operational circuit connected in series with a conduction path of the MOS transistor. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein each of the rows includes a trimming circuit connected in series, the trimming circuit comprising a nonvolatile memory cell and an operational circuit connected in series with a conduction path of the nonvolatile memory cell. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein each of the rows includes a trimming circuit connected in series, the trimming circuit comprising a breaker and an operational circuit connected in series with the breaker.

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