Ternary and Higher Multi-Value Digital Scramblers/Descramblers

Abstract

Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.

1 . A method of scrambling a plurality of n-state symbols with n>2, an n-state symbol being able to assume one of n states, comprising:
 inputting a first signal representing a first n-state symbol of the plurality of n-state symbols on a first input of a scrambling device also having a second input and an output;   inputting a second signal representing a second n-state symbol on the second input;   outputting an output signal representing a scrambled n-state symbol on the output;
 wherein the relationship between the first n-state symbol which may be called A, the second n-state symbol which may be called B and the scrambled n-state symbol which may be called C is determined by a commutative self reversing function, sc, that satisfies the following equations for all possible states of A and B: 
 (1) A sc B=C; 
 (2) C sc B=A; and 
 (3) A sc C=B; and 
   repeating the previous steps until all symbols of the plurality of n-state symbols have been scrambled.   
   
   
       2 . The method as claimed in  claim 1 , further comprising:
 inputting the output signal on an input of an n-state Linear Feedback Shift Register; and   generating the second signal on an output of the n-state Linear Feedback Shift Register.   
   
   
       3 . The method as claimed in  claim 1 , wherein the first and the second n-state symbol are represented by a first and a second plurality of binary signals. 
   
   
       4 . The method as claimed in  claim 1 , wherein the scrambling device is realized with binary circuitry. 
   
   
       5 . The method as claimed in  claim 1 , further comprising:
 inputting a third signal representing the scrambled n-state symbol on a first input of a descrambling device, the descrambling device also having a second input and an output;   inputting a fourth signal representing the second n-state symbol on the second input of the descrambling device;   outputting an output signal representing the first n-state symbol on the output of the descrambling device;
 wherein the descrambling device implements the commutative self reversing function, sc; and 
   repeating the previous steps until all symbols in the plurality of n-state symbols that have been scrambled are descrambled.   
   
   
       6 . The method as claimed in  claim 5 , further comprising:
 inputting also the third signal on an input of an n-state Linear Feedback Shift Register; and   generating the fourth signal on an output of the n-state Linear Feedback Shift Register.   
   
   
       7 . An apparatus for scrambling a plurality of n-state symbols including a first n-state symbol, into a plurality of scrambled n-state symbols, each n-state symbol enabled to assume one of n states with n>2, each n-state symbol being represented by a signal, comprising:
 a scrambling device having a first and a second input and an output, the first input enabled to receive a signal representing the first n-state symbol, the second input enabled to receive a signal representing a second n-state symbol and the output providing a signal representing a scrambled n-state symbol;
 wherein the relationship between the first n-state symbol which may be called A, the second n-state symbol which may be called B and the scrambled n-state symbol which may be called C is determined by a commutative self reversing function, sc, that satisfies the following equations for all possible states of A and B: 
 (1) A sc B=C; 
 (2) C sc B=A; and 
 (3) A sc C=B; and 
 wherein the scrambling device has a corresponding descrambling device that recovers the plurality of n-state symbols from the plurality of scrambled n-state symbols. 
   
   
   
       8 . The apparatus as claimed in  claim 7 , further comprising:
 an n-state Linear Feedback Shift Register (LFSR) including an input and an output, wherein the input of the n-state LFSR is enabled to receive the signal representing the scrambled n-state symbol and the output of the LFSR provides the signal representing the second n-state symbol.   
   
   
       9 . The apparatus as claimed in  claim 7 , wherein the first and the second n-state symbol are represented by a first and a second plurality of binary signals. 
   
   
       10 . The apparatus as claimed in  claim 7 , wherein the scrambling device is realized with binary circuitry. 
   
   
       11 . The apparatus as claimed in  claim 7 , further comprising:
 the descrambling device, having a first input enabled to receive a signal representing the scrambled n-state symbol, a second input enabled to receive a signal representing the second symbol, and an output enabled to provide the first n-state symbol;
 wherein the descrambling device implements the commutative self reversing function, sc. 
   
   
   
       12 . The apparatus as claimed in  claim 11 , further comprising:
 an n-state Linear Feedback Shift Register (LFSR) including an input and an output, wherein the input of the n-state LFSR is enabled to receive the signal representing the scrambled n-state symbol and the output of the LFSR provides the signal representing the second n-state symbol.   
   
   
       13 . The apparatus as claimed in  claim 7 , wherein the scrambled and the second n-state symbol are represented by a first and a second plurality of binary signals. 
   
   
       14 . The apparatus as claimed in  claim 7 , wherein the descrambling device is realized with binary circuitry. 
   
   
       15 . An apparatus for descrambling a plurality of scrambled n-state symbols including a first scrambled n-state symbol, each n-state symbol enabled to assume one of n states with n>2, each n-state symbol being represented by a signal, comprising:
 a descrambling device having a first and a second input and an output, the first input enabled to receive a signal representing the first scrambled n-state symbol, the second input enabled to receive a signal representing a second n-state symbol and the output providing a signal representing a descrambled n-state symbol;
 wherein the relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is determined by a commutative self reversing function, sc, that satisfies the following equations for all possible states of A and B: 
 (1) A sc B=C; 
 (2) C sc B=A; and 
 (3) A sc C=B. 
   
   
   
       16 . The apparatus as claimed in  claim 15 , further comprising:
 an n-state Linear Feedback Shift Register (LFSR) including an input and an output, wherein the input of the n-state LFSR is also enabled to receive the signal representing the descrambled n-state symbol and the output of the LFSR provides the signal representing the second n-state symbol.   
   
   
       17 . The apparatus as claimed in  claim 15 , wherein the first scrambled n-state symbol and the second n-state symbol are represented by a first and a second plurality of binary signals. 
   
   
       18 . The apparatus as claimed in  claim 15 , wherein the descrambling device is realized with binary circuitry. 
   
   
       19 . The apparatus as claimed in  claim 15 , further comprising a corresponding scrambling apparatus, including:
 a scrambling device, having a first input enabled to receive a signal representing a first n-state symbol, a second input enabled to receive a signal representing the second symbol, and an output enabled to provide the first scrambled n-state symbol;
 wherein the scrambling device implements the commutative self reversing function, sc. 
   
   
   
       20 . The apparatus as claimed in  claim 19 , further comprising:
 an n-state Linear Feedback Shift Register (LFSR) including an input and an output, wherein the input of the n-state LFSR is enabled to receive the signal representing the scrambled n-state symbol and the output of the LFSR provides the signal representing the second n-state symbol.