Semiconductor memory device configured to reduce current consumption associated with critical evaluating of data write operations

Abstract

A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass.

1 . A semiconductor memory device, comprising:
 write pass corresponding to first pad and transferring any one of general data and representative data corresponding to specific mode; and   a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific mode and upon deviating from the specific mode, interrupting the routing of the general data to the transfer pass.   
   
   
       2 . The semiconductor memory device set forth in  claim 1 , wherein the general data are data input in a write operation mode and the representative data are data input in a parallel test mode or a standby mode. 
   
   
       3 . The semiconductor memory device set forth in  claim 2 , wherein the routing controller, when in the parallel test mode, routes the representative data to the transfer pass and the routing controller, when in the write operation mode, interrupts the routing of the general data to the transfer pass. 
   
   
       4 . The semiconductor memory device set forth in  claim 2 , wherein the transfer pass include an off chip driver controller which in the standby mode receives the representative data to control impedance of a data output driver. 
   
   
       5 . The semiconductor memory device set forth in  claim 4 , wherein the routing controller, when in the standby mode, routes the representative data to the off chip driver controller and the routing controller, when in the write operation, interrupts the routing of the general data to the off chip driver controller. 
   
   
       6 . A semiconductor memory device, comprising:
 first pad receiving first general data;   second pad receiving any one of second general data and representative data corresponding to specific mode;   data alignment unit aligning the data input from the first and second pad, respectively, being matched with a burst sequence;   a routing controller routing the aligned representative data to transfer pass corresponding to the first pad and the second pad directed by the specific mode, and upon deviating from the specific mode, and interrupting the routing of the aligned second general data to the transfer pass corresponding to the first pad;   multiplexer selecting and transferring any one of the aligned first general data and the aligned representative data according to the specific mode; and   sense amplifier amplifying the aligned second general data and data transferred through the multiplexer and transferring the amplified data to global data line.   
   
   
       7 . The semiconductor memory device set forth in  claim 6 , wherein when in the write operation the first and second general data are input to the first and second pad respectively and when in a parallel test mode or a standby mode the representative data are representatively input from the second pad. 
   
   
       8 . The semiconductor memory device set forth in  claim 7 , wherein when in the parallel test mode the routing controller transfers to the aligned representative data to the respective multiplexer and when in the write operation the routing controller interrupts the transfer of the aligned second general data to the respective multiplexer. 
   
   
       9 . The semiconductor memory device set forth in  claim 8 , wherein the routing controller includes a logic combination unit which logically combines a parallel test signal determining the parallel test mode and the aligned representative data or logically combines the parallel test signal and the aligned second general data, and the routing is controlled by the logically combination of the logic combination unit. 
   
   
       10 . The semiconductor memory device set forth in  claim 7 , further comprising an off chip driver controller, when in the standby mode, which receives the aligned representative data to control an impedance of a data output driver. 
   
   
       11 . The semiconductor memory device set forth in  claim 10 , wherein when in the standby mode the routing controller transfers the aligned representative data to the off chip driver controller and when in the write operation mode the routing controller interrupts the transfer of the aligned second general data to the off chip driver 
   
   
       12 . The semiconductor memory device set forth in  claim 11 , wherein the routing controller includes a logic combination unit which logically combines a ras idle signal determining the standby mode and the aligned representative data or logically combines the ras idle signal and the aligned second general data, and the routing is controlled by the logically combination of the logic combination unit. 
   
   
       13 . The semiconductor memory device set forth in  claim 11 , wherein when in the write operation the routing controller interrupts the transfer of the aligned second general data to the multiplexer and to the off chip driver controller; when in the parallel test mode the routing controller transfers the aligned representative data to the respective multiplexer; and when in the standby mode the routing controller transfers the aligned representative data to the off chip driver controller. 
   
   
       14 . The semiconductor memory device set forth in  claim 13 , wherein the routing controller includes:
 a first logic combination unit which logically combines a parallel test signal determining the parallel test mode and a ras idle signal determining the standby mode; and   a second logic combination unit which logically combines an output of the first logic combination unit and the aligned representative data or combines the output of the first logic combination unit and the second general data,   wherein the routing is controlled by the logically combination of the second logic combination unit.   
   
   
       15 . The semiconductor memory device set forth in  claim 6 , wherein when in the write operation the multiplexer selects and transfers the aligned first general data; and when in the parallel test mode or the standby mode the multiplexer selects and transfers the aligned representative data routed to the transfer pass.