Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom

Abstract

A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

1 . A semiconductor device, comprising:
 a substrate formed of semiconductor material;   a source region formed in the substrate and doped with a first type of impurities;   a first polysilicon region in ohmic contact with the source region;   a drain region formed in the substrate and doped with the first type of impurities, the drain region spaced apart from the source region;   a second polysilicon region in ohmic contact with the drain region;   a gate region formed in the substrate and doped with a second type of impurities;   a third polysilicon region in ohmic contact with the gate region;   a conducting region formed between the source region and the drain region and doped with the first type of impurities, wherein the conducting region is formed from a material having a first thermal expansion coefficient and is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state, and wherein the conducting region comprises a channel region abutting the gate region; and   a stress layer abutting the conducting region, wherein the stress layer is formed from a material having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient and wherein the stress layer applies a stress to the conducting region that strains at least a portion of the conducting region.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the stress layer comprises:
 a first portion formed between the first polysilicon region and the third polysilicon region; and   a second portion formed between the second polysilicon region and the third polysilicon region.   
   
   
       3 . The semiconductor device of  claim 2 , wherein:
 the first portion of the stress layer applies a first force to the conducting region; and   the second portion of the stress layer applies a second force to the conducting region having an opposite direction to the first force.   
   
   
       4 . The semiconductor device of  claim 1 , wherein the stress layer comprises silicon nitride. 
   
   
       5 . The semiconductor device of  claim 1 , further comprising a gate contact formed on the second polysilicon region having an ohmic connection to the gate region through the second polysilicon region. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the stress applied to the conducting region increases a mobility of charge carriers in at least a portion of the conducting region. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the semiconductor device comprises a junction field effect transistor (JFET). 
   
   
       8 . A method for fabricating a semiconductor device, comprising:
 forming a source region doped with a first type of impurities in a semiconductor substrate;   forming a first polysilicon region in ohmic contact with the source region;   forming a drain region doped with the first type of impurities in the semiconductor substrate, the drain region spaced apart from the source region;   forming a second polysilicon region in ohmic contact with the drain region;   forming a conducting region between the source region and the drain region from a first material having a first thermal expansion coefficient, the conducting region doped with the first type of impurities and operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state;   forming a channel region in the conducting region;   forming a gate region doped with a second type of impurities, the gate region abutting the channel region;   forming a third polysilicon region in ohmic contact with the gate region; and   forming a stress layer abutting the conducting region, wherein the stress layer comprises a second material having a second thermal expansion coefficient greater than the first thermal expansion coefficient and applies a stress to the conducting region that strains at least a portion of the conducting region.   
   
   
       9 . The method of  claim 8 , wherein forming the stress layer comprises:
 forming a first portion of the stress layer between the first polysilicon region and the third polysilicon region; and   forming a second portion of the stress layer between the second polysilicon region and the third polysilicon region.   
   
   
       10 . The method of  claim 9 , wherein:
 forming a first portion of the stress layer comprises forming a first portion that applies a first force to the conducting region; and   forming the second portion of the stress layer comprises forming a second portion that applies a second force to the conducting region in an opposite direction to the first force.   
   
   
       11 . The method of  claim 8 , wherein forming the stress layer comprises depositing a layer of silicon nitride. 
   
   
       12 . The method of  claim 8 , further comprising forming a gate contact on the second polysilicon region, the gate contact having an ohmic connection to the gate region through the second polysilicon region. 
   
   
       13 . The method of  claim 8 , wherein the stress applied to the conducting region increases a mobility of charge carriers in at least a portion of the conducting region. 
   
   
       14 . The method of  claim 8 , wherein the method of forming a semiconductor device comprises a method of forming a junction field effect transistor (JFET). 
   
   
       15 . A method of operating a semiconductor device, comprising:
 applying a stress to a conducting region formed in a substrate of a semiconductor device, the stress increasing a mobility of charge carriers in at least a portion of the conducting region;   applying a voltage differential across a gate region and a source region formed in the substrate, wherein the gate region abuts a channel region formed in the conducting region;   in response to the voltage differential between the gate region and the source region being greater than or equal to an operating voltage of the semiconductor device, allowing current to flow between the source region and a drain region through the conducting region; and   in response to the voltage differential between the gate region and the source region being less than the operating voltage, preventing current from flowing between the source region and the drain region through the conducting region.   
   
   
       16 . The method of  claim 15 , wherein applying a stress to the conducting region comprises applying a stress to the conducting region using a stress layer formed along at least one boundary of the conducting region. 
   
   
       17 . The method of  claim 16 , wherein:
 the substrate comprises material having a first thermal expansion coefficient; and   the stress layer comprises material having a second thermal expansion coefficient.   
   
   
       18 . The method of  claim 16 , wherein the stress layer comprises silicon nitride. 
   
   
       19 . The method of  claim 15 , wherein applying a stress to the conducting region comprises applying a tensile stress to the conducting region. 
   
   
       20 . The method of  claim 15 , wherein applying a stress to the conducting region comprises applying a compressive stress to the conducting region. 
   
   
       21 . The method of  claim 15 , wherein applying a voltage differential across the gate region and the source region comprises:
 applying a first voltage to the gate region through a first polysilicon region in ohmic contact with the gate region; and   applying a second voltage to the source region through a second polysilicon region in ohmic contact with the source region.   
   
   
       22 . The method of  claim 15 , wherein the semiconductor device comprises a junction field effect transistor (JFET). 
   
   
       23 . An electronic device, comprising:
 a substrate formed of semiconductor material;   a first semiconductor device formed in the substrate, comprising:
 a first source region doped with a first type of impurities; 
 a first drain region doped with the first type of impurities, the first drain region spaced apart from the first source region; 
 a first gate region doped with a second type of impurities; 
 a first conducting region formed between the first source region and the first drain region and doped with the first type of impurities, the first conducting region operable to conduct current between the first drain region and the first source region when the first semiconductor device is operating in an on state, wherein the first conducting region comprises a first channel region abutting the first gate region; and 
 a first stress layer abutting the first conducting region, wherein the first stress layer applies a stress to the first conducting region that strains at least a portion of the first conducting region; and 
   a second semiconductor device formed in the substrate, comprising:
 a second source region doped with the second type of impurities; 
 a second drain region doped with the second type of impurities, the second drain region spaced apart from the second source region; 
 a second gate region doped with the first type of impurities; 
 a second conducting region formed between the second source region and the second drain region and doped with the second type of impurities, the second conducting region operable to conduct current between the second drain region and the second source region when the second semiconductor device is operating in an on state, wherein the second conducting region comprises a second channel region abutting the second gate region; and 
 a second stress layer abutting the second conducting region, wherein the second stress layer applies a stress to the second conducting region that strains at least a portion of the second conducting region. 
   
   
   
       24 . A method of fabricating an electronic device, comprising:
 forming a first semiconductor device in a semiconductor substrate by:
 forming a first source region doped with a first type of impurities; 
 forming a first drain region doped with the first type of impurities, the first drain region spaced apart from the first source region; 
 forming a first conducting region between the first source region and the first drain region, the first conducting region doped with the first type of impurities and operable to conduct current between the first drain region and the first source region when the first semiconductor device is operating in an on state; 
 forming a first channel region in the first conducting region; 
 forming a first gate region doped with a second type of impurities, the first gate region abutting the first channel region; and 
 forming a first stress layer abutting the first conducting region, wherein the first stress layer applies a stress to the first conducting region that strains at least a portion of the first conducting region; and 
   forming a second semiconductor device in the semiconductor substrate by:
 forming a second source region doped with the second type of impurities; 
 forming a second drain region doped with the second type of impurities, the second drain region spaced apart from the second source region; 
 forming a second conducting region between the second source region and the second drain region, the second conducting region doped with the second type of impurities and operable to conduct current between the second drain region and the second source region when the second semiconductor device is operating in an on state; 
 forming a second channel region in the second conducting region; 
 forming a second gate region doped with a first type of impurities, the second gate region abutting the second channel region; and 
 forming a second stress layer abutting the second conducting region, wherein the second stress layer applies a stress to the second conducting region that strains at least a portion of the first conducting region.