Flash EEPROM device and method for fabricating the same

Abstract

In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed in the word line direction, an interlayer polysilicon oxide film formed on a floating gate, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N + region formed in the semiconductor substrate under the source and drain electrodes, and a metal silicide film formed on an upper surface of the control gate.

1 . A flash EEPROM device, comprising:
 a semiconductor substrate having an active area defined in a bit line direction and a word line direction;   a plurality of floating gates formed on the active area of said semiconductor substrate in the word line direction;   an interlayer polysilicon oxide film formed on said at least one of the plurality of floating gates;   a control gate formed on said interlayer polysilicon oxide film;   source and drain electrodes disposed between adjacent floating gates in the word line direction;   a buried N +  region formed in said semiconductor substrate under said source and drain electrodes; and   a metal silicide film formed on an upper surface of said control gate.   
   
   
       2 . The flash EEPROM device of  claim 1 , further comprising:
 a gate insulating film formed on an upper surface of said source and drain electrodes.   
   
   
       3 . The flash EEPROM device of  claim 2 , wherein said control gate is formed on said at least one of the plurality of floating gates and on said source and drain electrodes in the word line direction of said semiconductor substrate. 
   
   
       4 . The flash EEPROM device of  claim 3 , wherein said gate insulating film is disposed between said control gate and said source and drain electrodes. 
   
   
       5 . The flash EEPROM device of  claim 1 , further comprising:
 a tunneling oxide film formed on said semiconductor substrate to be disposed under said at least one of the plurality of floating gates.   
   
   
       6 . The flash EEPROM device of  claim 1 , further comprising:
 sidewall spacers disposed at opposite sides of said at least one of the plurality of floating gates.   
   
   
       7 - 12 . (canceled) 
   
   
       13 . The device of  claim 6 , wherein the control gate is formed between the sidewall spacers. 
   
   
       14 . The device of  claim 6 , wherein the interlayer polysilicon oxide film is formed between the sidewall spacers. 
   
   
       15 . The device of  claim 6 , wherein the interlayer polysilicon oxide film is formed between the sidewall spacers and the control gate is formed on the interlayer polysilicon oxide film between the sidewall spacers.