Depletion Mode Field Effect Transistor for ESD Protection

Abstract

The object of this invention is to present a field effect transistor by which the drain capacitance per unit gate width can be reduced. The gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14, drain region 18 D (D) is formed inside the gate electrode, and source regions 18 S (S) are formed in the respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.

1 . Claim  1  is a field effect transistor, comprising:
 a semiconductor region of a first conductivity type with a channel formation region;   a gate electrode that is formed in a pattern with a plurality of sides on a gate insulation film above the channel formation region of the first semiconductor region;   a drain region that is formed in the first semiconductor region within an inner region of the gate electrode; and   second-conductivity type source regions that are formed in the first semiconductor region in regions opposite to said inner region of the gate electrode in predetermined widths.   
   
   
       2 . The field effect transistor of  claim 1 , wherein the gate electrode is formed in a two-dimensional grid pattern, and the drain region and the source region are formed alternately and repeatedly in two dimensions in regions of the two-dimensional grid pattern. 
   
   
       3 . The field effect transistor of  claim 2 , wherein back gates are formed in the first semiconductor region. 
   
   
       4 . The field effect transistor of  claim 3 , wherein the back gates and the source regions are connected to each other, and a common potential is applied to them. 
   
   
       5 . The field effect transistor of  claim 4 , wherein the first-conductivity type is p-type and the second-conductivity type is n-type. 
   
   
       6 . The field effect transistor of  claim 5 , wherein a second-conductivity type channel region is formed in the channel formation region of the semiconductor region. 
   
   
       7 . An ESD depletion mode field effect transistor, comprising:
 a semiconductor layer of a first conductivity type formed on a semiconductor substrate;   a square drain region of a second conductivity type formed in the first semiconductor layer;   a plurality of source regions of a second conductivity type formed in first semiconductor layer at a predetermined distance from the drain region;   a grid-shaped gate electrode formed on a gate insulating layer above a channel region of the first semiconductor layer, which is positioned between the drain region and the multiple source regions and surrounding the drain region, wherein the multiple source regions are provided at positions that correspond to respective sides of the drain region; and   the multiple source regions are connected to each other electrically.   
   
   
       8 . The transistor of  claim 7  further comprising:
 the drain region, the multiple source regions, and the gate electrode all formed in a repetitive pattern;   the drain regions formed in the repetitive pattern being connected to each other electrically; and   the multiple source regions formed in the repetitive pattern being connected to each other electrically.   
   
   
       9 . The transistor of  claim 7  further comprising:
 a back gate region of a first conductivity type formed in the first semiconductor layer; and   the multiple source regions and the back gate region connected to each other electrically.   
   
   
       10 . The transistor of  claim 9 , wherein the channel region comprises a first-conductivity type semiconductor layer formed in the first semiconductor layer. 
   
   
       11 . The transistor of  claim 10 , wherein the first-conductivity type is p-type and the second-conductivity type is n-type.