US2009072325A1PendingUtilityA1

Metal-oxide semiconductor transistor

Assignee: WU CHIH-CHIANGPriority: Jan 31, 2007Filed: Nov 23, 2008Published: Mar 19, 2009
Est. expiryJan 31, 2027(~0.5 yrs left)· nominal 20-yr term from priority
H10D 64/0112H10W 10/0145H10W 10/17H10D 62/021H10D 30/0212H10D 30/0227H10D 30/797
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Claims

Abstract

A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar.

Claims

exact text as granted — not AI-modified
1 . A metal-oxide semiconductor (MOS) transistor comprising:
 a gate structure positioned in an active area defined in a substrate;   a recessed source/drain; and   an asymmetric shallow trench isolation (STI) for electrically isolating the active areas, a surface of the asymmetric STI and the substrate being coplanar.   
     
     
         2 . The MOS transistor of  claim 1  wherein the gate structure further comprises:
 a gate dielectric layer;   a gate conductive layer positioned on the gate dielectric layer;   a spacer positioned on sidewalls of the gate conductive layer; and   lightly doped drains (LDDs) respectively positioned in the substrate on two sides of the gate conductive layer.   
     
     
         3 . The MOS transistor of  claim 1  wherein the asymmetric STI is a multiple STI. 
     
     
         4 . The MOS transistor of  claim 3  wherein the multiple STI comprises a main STI and a sub-STI positioned on at least one side of the main STI. 
     
     
         5 . The MOS transistor of  claim 4 , wherein a surface of the main STI and a surface of the sub-STI are coplanar. 
     
     
         6 . The MOS transistor of  claim 4  wherein the sub-STI comprises silicon dioxide, silicon oxynitride, or silicon nitride. 
     
     
         7 . The MOS transistor of  claim 1  wherein the gate structure is a gate structure of a PMOS transistor. 
     
     
         8 . The MOS transistor of  claim 7 , wherein the recessed source/drain comprises silicon germanium (SiGe). 
     
     
         9 . The MOS transistor of  claim 1 , wherein the gate structure is a gate structure of an NMOS transistor. 
     
     
         10 . The MOS transistor of  claim 9 , wherein the recessed source/drain comprises silicon carbide (SiC).

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