Direct access of cache lock set data without backing memory

Abstract

Apparatus and system for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

1 . A processor, comprising:
 one or more processing cores;   at least one shared cache accessible by the one or more processing cores, the shared cache comprising a plurality of cache lines allocatable to a lock set, wherein data stored in cache lines allocated to the lock set is transferred directly to a processing core within an external processor without writing the data to external memory, and wherein the plurality of cache lines comprise only a limited portion of the cache; and   a pointer containing a value indicating a first address corresponding to the lock set, up to which the external processor has read data,   wherein data stored in a cache line allocated to the lock set is transferred to the external processor upon receiving a request from the external processor, the request being transferred to the processor upon determining that a second address supplied with the request falls within an address range of the lock set.   
   
   
       2 . The processor of  claim 1 , wherein:
 the shared cache comprises a plurality of associative sets; and   a portion of all of one or more of the associative sets may be allocated to the lock set.   
   
   
       3 . The processor of  claim 1 , wherein the one or more processing cores comprises a plurality of processing cores, each having an associated primary cache. 
   
   
       4 . A system, comprising:
 main memory;   a memory controller for accessing the main memory;   a first processor capable of accessing the main memory via the memory controller, the first processor having at least one cache capable of being placed in a lock set mode wherein a plurality of cache lines of the cache are allocated to a lock set, wherein the plurality of cache lines comprise only a limited portion of the cache; and   a second processor capable of accessing and processing data stored in one or more cache lines allocated to a lock set of the cache on the first processor without the data being written out to main memory,
 wherein the first processor is a central processing unit (CPU) having one or more processor cores that share the cache and the second processor is a graphics processing unit (GPU); and the memory controller is integrated with the GPU, and wherein: 
 the second processor is configured to generate a request for data to the memory controller; and 
 the memory controller is configured to:
 determine whether an address supplied with the request falls within a first address range or a second address range, the first address range being reserved for the lock set and the second address range being reserved for the main memory; 
 upon determining that the address falls within the first address range, route the request to the first processor; and 
 upon determining that the address falls within the second address range, route the request to the main memory.