Differential Low Noise Amplifier (LNA) With Common Mode Feedback And Gain Control

Abstract

A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal.

1 . An amplifier with gain control, comprising:
 a) an input stage including:
 i) a first differential input including a first input transistor for receiving a true input signal and a second input transistor for receiving a complementary input signal, said complementary input signal being the logic complement of said true signal, 
 ii) a first current source coupled to said first input transistor and to said second input transistor, 
 iii) a first current load receiving a bias voltage and coupling said first input transistor to a first power rail, and a second current load receiving said bias voltage and coupling said second input transistor to said power rail; 
 iv) a first common mode feedback transistor coupling said first current source to a second power rail and configured to limit current to said first current source in response to an output of said first input transistor, a second common mode feedback transistor coupling said first current source to said second power rail and configured to limit current to said first current source in response to an output of said second input transistor, the outputs of said first and second input transistors constituting an intermediate differential amplified signal; 
 v) a first gain control transistor coupled in parallel to said first input transistor, said first gain control transistor being responsive to a gain control input, and a second gain control transistor coupled in parallel to said second input transistor, said second gain control transistor being responsive to said gain control input. 
   
   
   
       2 . The amplifier with gain control of  claim 1 , further comprising:
 b) an additional stage, including
 i) a second differential input configured to receive said intermediate differential amplified signal from said input stage, said second differential input including a third input transistor and a fourth input transistor; 
 ii) a second current source coupled to said third input transistor and to said fourth input transistor, 
 iii) a third current load receiving said bias voltage and coupling said third input transistor to said first power rail, and a fourth current load receiving said bias voltage and coupling said fourth input transistor to said first power rail; 
 iv) a second common mode feedback transistor coupling said second current source to said second power rail and configured to limit current to said second current source in response to an output of said third input transistor, a fourth common mode feedback transistor coupling said current source to said second power rail and configured to limit current to said second current source in response to an output of said fourth input transistor, the outputs of said third and fourth input transistors constituting an amplified output; 
 v) a third gain control transistor coupled in parallel to said third input transistor, said third gain control transistor being responsive to said gain control input, and a fourth gain control transistor coupled in parallel to said fourth input transistor, said fourth gain control transistor being responsive to said gain control input; 
   c) a first bias circuit configured to provide said bias voltage to said first, second, third and fourth current loads; and   d) a second bias circuits configured to bias said first current source.   
   
   
       3 . The amplifier with gain control of  claim 2 , wherein the intermediate differential output of the input stage is capacitively coupled to the second differential input of the additional stage. 
   
   
       4 . The amplifier with gain control of  claim 1 , further comprising an enable input configured to ground said bias voltage when said amplifier is disabled. 
   
   
       5 . The amplifier with gain control of  claim 1 , wherein said first power rail is a ground power rail. 
   
   
       6 . The amplifier with gain control of  claim 2 , wherein said first bias circuit is configured to receive a bias current for generation of said bias voltage. 
   
   
       7 . The amplifier with gain control of  claim 2 , wherein said first, second, third and fourth current loads are first, second, third and fourth load transistors, respectively. 
   
   
       8 . The amplifier with gain control of  claim 2 , wherein said first, second, third and fourth load transistors are NMOS transistors. 
   
   
       9 . The amplifier with gain control of  claim 2 , wherein said first and second current sources comprise first and second current source transistors, respectively. 
   
   
       10 . The amplifier with gain control of  claim 9 , wherein said first and second current source transistors are PMOS transistors. 
   
   
       11 . The amplifier with gain control of  claim 2 , wherein said first, second, third and fourth common mode feedback transistors are PMOS transistors. 
   
   
       12 . The amplifier with gain control of  claim 1 , wherein the drain electrode of said first gain control transistor is coupled to the drain electrode of said first input transistor, the source electrode of said first gain control transistor is coupled to the source electrode of said first input transistor, the drain electrode of said second gain control transistor is coupled to the drain electrode of said second input transistor, and the source electrode of said second gain control transistor is coupled to the source electrode of said second input transistor, 
   
   
       13 . The amplifier with gain control of  claim 2 , wherein the drain electrode of said third gain control transistor is coupled to the drain electrode of said third input transistor, the source electrode of said third gain control transistor is coupled to the source electrode of said third input transistor, the drain electrode of said fourth gain control transistor is coupled to the drain electrode of said fourth input transistor, and the source electrode of said fourth gain control transistor is coupled to the source electrode of said fourth input transistor, 
   
   
       14 . A method of controlling a gain in a low noise amplifier (LNA), comprising the steps of:
 a) receiving a differential signal at an input stage, said input stage including:
 i) a first differential input including a first input transistor for receiving a true input signal and a second input transistor for receiving a complementary input signal, said complementary input signal being the logic complement of said true signal, 
 ii) a first current source coupled to said first input transistor and to said second input transistor, 
 iii) a first current load receiving a bias voltage and coupling said first input transistor to a first power rail, and a second current load receiving said bias voltage and coupling said second input transistor to said power rail; and 
 iv) a first common mode feedback transistor coupling said first current source to a second power rail and configured to limit current to said first current source in response to an output of said first input transistor, a second common mode feedback transistor coupling said first current source to said second power rail and configured to limit current to said first current source in response to an output of said second input transistor, the outputs of said first and second input transistors constituting an intermediate differential amplified signal; and 
   b) modifying said gain by varying a voltage of a gain control input, said gain control input being coupled to control inputs of first and second gain control transistors, said first gain control transistor being coupled in parallel to said first input transistor, and said second gain control transistor being coupled in parallel to said second input transistor.   
   
   
       15 . The method of  claim 14 , further comprising:
 c) applying said intermediate differential amplified signal to a second differential input of an additional stage, said additional stage including:
 i) a third input transistor and a fourth input transistors constituting said second differential input of said additional stage; 
 ii) a second current source coupled to said third input transistor and to said fourth input transistor, 
 iii) a third current load receiving said bias voltage and coupling said third input transistor to said first power rail, and a fourth current load receiving said bias voltage and coupling said fourth input transistor to said first power rail; 
 iv) a second common mode feedback transistor coupling said second current source to said second power rail and configured to limit current to said second current source in response to an output of said third input transistor, a fourth common mode feedback transistor coupling said current source to said second power rail and configured to limit current to said second current source in response to an output of said fourth input transistor, the outputs of said third and fourth input transistors constituting an amplified output; 
   d) further modifying said gain applying said gain control input to control inputs of third and fourth gain control transistors, said third gain control transistor being coupled in parallel to said third input transistor, and said fourth gain control transistor being coupled in parallel to said fourth input transistor.   e) providing said first bias voltage to said first, second, third and fourth current loads; and   f) biasing said first and second current sources.   
   
   
       16 . The method of  claim 15  further comprising, capacitively coupling the intermediate differential output of the input stage to the second differential input of the additional stage. 
   
   
       17 . The method of  claim 15 , further comprising grounding said bias voltage in response to an enable input. 
   
   
       18 . The method of  claim 15 , wherein said bias voltage is generated in response to a first bias current.