Method of operating non-volatile memory array

Abstract

A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

1 . A method of operating a non-volatile memory array, the non-volatile memory array comprising:
 a substrate;   a plurality of rows of memory cells, wherein each row of memory cells includes a plurality of stacked gate structures separated from each other by a gap, and each stacked gate structure includes a select gate, a plurality of floating gates disposed in the gap between every pair of neighboring stacked gate structures, a plurality of control gates disposed between every pair of neighboring stacked gate structures and positioned above the floating gate, and a pair of source/drain region disposed in the substrate on each outer side of the row of the memory cells;   a plurality of control gate lines connected with the control gates in the same row;   a plurality of select gate lines connected with the select gates in the same column;   a plurality of source lines connected with the source regions in the same column; and   a plurality of drain lines connected with the drain regions in the same column, the operating method comprising:
 applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate; and 
 grounding the drain lines so that source-side injection (SSI) is triggered to inject electrons into the floating gate of the selected memory cell in a programming operation. 
   
   
   
       2 . The method of  claim 1 , further comprising:
 applying 0V voltage to the source lines, 4.5V voltage to the select gate lines, 3V voltage to the selected control gate line and 2V voltage to the drain lines to read data from the memory cells.   
   
   
       3 . The method of  claim 1 , further comprising:
 applying −20V voltage to the control gate lines and 0V voltage to the substrate so that the Fowler-Nordheim (F-N) tunneling effect can be induced to erase all data within the memory array.