Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

1 . A semiconductor memory device, comprising a plurality of transistors having a stacked-gate structure, each transistor including;
 a semiconductor substrate,   a gate insulator formed on said semiconductor substrate,   a lower gate formed on said semiconductor substrate with said gate insulator interposed,   an intergate insulator formed on said lower gate, and   an upper gate formed and silicided on said lower gate with said intergate insulator interposed,   a portion of said transistors having an aperture formed through said intergate insulator to connect said lower gate with said upper gate and further including a block film composed of an insulator and formed smaller than said upper gate and larger than said aperture above said upper gate to cover said aperture.   
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein at least a portion of said upper gate is fully silicided in a film thickness range. 
   
   
       3 . The semiconductor memory device according to  claim 1 , wherein metal atoms in said silicided upper gate of said transistor are not diffused into said gate insulator through said aperture. 
   
   
       4 . The semiconductor memory device according to  claim 1 , wherein said aperture is formed almost at the center of the upper surface of said lower gate. 
   
   
       5 . The semiconductor memory device according to  claim 1 , wherein said upper gate is composed of a nickel silicide, a tungsten silicide, a cobalt silicide or a titanium silicide. 
   
   
       6 . A semiconductor memory device, comprising:
 a plurality of memory cells, each including;
 a semiconductor substrate, 
 a gate insulator formed on said semiconductor substrate, 
 a lower gate serving as a floating gate formed on said semiconductor substrate with said gate insulator interposed, 
 an intergate insulator formed on said lower gate, and 
 an upper gate serving as a control gate formed and silicided on said lower gate with said intergate insulator interposed; and 
   a plurality of transistors formed together with said memory cells, each transistor including;
 said semiconductor substrate, 
 said gate insulator, 
 said lower gate, 
 said intergate insulator, and 
 said upper gate, 
   said transistor having an aperture formed through said intergate insulator to connect said lower gate with said upper gate and further including a block film composed of an insulator and formed smaller than said upper gate and larger than said aperture above said upper gate to cover said aperture.   
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein at least a portion of said upper gate is fully silicided in a film thickness range. 
   
   
       8 . The semiconductor memory device according to  claim 6 , wherein metal atoms in said silicided upper gate of said transistor are not diffused into said gate insulator through said aperture. 
   
   
       9 . The semiconductor memory device according to  claim 6 , further comprising a gate isolation layer arranged to isolate said upper and lower gates between memory cells adjoining in a gate length direction,
 wherein said upper and lower gates and said gate isolation layer are formed in a measurement ratio of almost 1:1 in said gate length direction.   
   
   
       10 . The semiconductor memory device according to  claim 6 , wherein said upper gate of each of said memory cells is formed extending in a gate width direction and shared by said memory cells adjoining in said gate width direction. 
   
   
       11 . The semiconductor memory device according to  claim 6 , wherein said upper gate of said transistor is formed extending in a gate width direction and shared by said transistors adjoining in said gate width direction. 
   
   
       12 . The semiconductor memory device according to  claim 6 , wherein said aperture is formed almost at the center of the upper surface of said lower gate. 
   
   
       13 . The semiconductor memory device according to  claim 6 , wherein said upper gate is composed of a nickel silicide, a tungsten silicide, a cobalt silicide or a titanium silicide. 
   
   
       14 . The semiconductor memory device according to  claim 6 , wherein said memory cells are connected in series, of which both ends are connected to said transistors to configure a NAND-type flash memory. 
   
   
       15 . A method of manufacturing a semiconductor memory device, comprising:
 forming a gate insulator on a semiconductor substrate;   forming a first conductive film on said gate insulator;   forming an intergate insulator on said first conductive film;   selectively forming an aperture by etching through said intergate insulator in part of a region for use in formation of a transistor;   forming a second conductive film on said intergate insulator;   forming a first insulator above said second conductive film;   forming a block film larger than said aperture to cover said aperture by selectively removing part of said first insulator;   forming a sidewall composed of a second insulator on the sides of said block film and forming a gate pattern composed of said second insulator in a region for use in formation of control gates of memory cells;   selectively removing said second conductive film, said intergate insulator and said first conductive film by etching with a mask of said block film, said sidewall and said gate pattern to form gates of said memory cell and said transistor;   burying a third insulator around said formed gates;   removing said second insulator after burying said third insulator; and   siliciding said second conductive film by depositing a siliciding metal on an upper surface of a portion of the gates of said memory cell and said transistor from which said second insulator has been removed.   
   
   
       16 . The method of manufacturing a semiconductor memory device according to  claim 15 , further comprising forming a line pattern composed of said first insulator at a position between gates of said memory cells together with the step of forming a block film,
 wherein forming a sidewall and a gate pattern includes depositing said second insulator on said block film and said line pattern, then etching back said deposited second insulator, and selectively removing said first insulator from a region for use in formation of said memory cells, thereby forming said gate pattern having a smaller pattern pitch than the pattern pitch of said line pattern of said first insulator.   
   
   
       17 . The method of manufacturing a semiconductor memory device according to  claim 16 , wherein forming a line pattern includes forming said line pattern with a ratio of about 1:3 between said line pattern and a space pattern between said line patterns, and
 forming a gate pattern includes forming said gate pattern on the side wall of said line pattern with a ratio of about 1:1 between said gate pattern measurement and said line pattern measurement.   
   
   
       18 . The method of manufacturing a semiconductor memory device according to  claim 15 , wherein said siliciding metal is nickel, tungsten, cobalt or titanium. 
   
   
       19 . The method of manufacturing a semiconductor memory device according to  claim 15 , wherein siliciding said second conductive film includes siliciding entirely said second conductive film of said memory cells. 
   
   
       20 . The method of manufacturing a semiconductor memory device according to  claim 15 , wherein said first insulator is silicon oxide and said second insulator is silicon nitride.