Universal serial bus hub with shared high speed handler

Abstract

A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to store specific transactions (comprising data) received through the upstream port. Each respective downstream data handler is configured to access respective transactions of the stored specific transactions intended for the downstream port associated with the respective downstream data handler, and transmit to its associated respective downstream port the data comprised in its respective transactions. Accordingly, the upstream data handler is shared between the various downstream data handlers.

1 . A device, comprising:
 an upstream port configured to operate at a first data transfer rate;   a plurality of downstream ports configured to operate at a different data transfer rate than the first data transfer rate;   an upstream data handler coupled to the upstream port and configured to store specific transactions received through the upstream port, wherein the specific transactions comprise data;   a plurality of downstream data handlers, wherein each respective downstream data handler of the plurality of downstream data handlers is:
 associated with a respective downstream port of the plurality of downstream ports; 
 operable to access respective transactions of the stored specific transactions, wherein the respective transactions are intended for the respective downstream port associated with the respective downstream data handler; and 
 transmit to its associated respective downstream port, at the different data transfer rate, the data comprised in its respective transactions; 
   wherein the specific transactions comprise transactions defined by USB (Universal Serial Bus) protocol.   
   
   
       2 . The device of  claim 1 , wherein the upstream data handler is configured to accept the specific transactions through the upstream port at the first data rate. 
   
   
       3 . The device of  claim 1 , wherein the upstream data handler is configured to store the data comprised in the specific transactions in a plurality of memory devices; and
 wherein each of the plurality of memory devices is associated with a respective one of the plurality of downstream data handlers.   
   
   
       4 . The device of  claim 1 , wherein the upstream data handler is configured to store the data comprised in the specific transactions in a shared memory device; and
 wherein each respective downstream data handler is configured to retrieve the data comprised in its respective transactions from the shared memory device for output via its associated respective downstream port.   
   
   
       5 . The device of  claim 1 , wherein each respective downstream data handler is configured to provide data to its associated respective downstream port substantially simultaneously with another one of the plurality of downstream data handlers providing data to its associated respective downstream port. 
   
   
       6 . The device of  claim 1 , wherein the specific transactions comprise USB high-speed split transactions. 
   
   
       7 . The device of  claim 6 , wherein the high-speed split transactions comprise one or more of:
 start-split transactions; or   complete-split transactions.   
   
   
       8 . The device of  claim 7 , wherein the upstream data handler is configured to accept the start-split transactions and respond to the complete-split transactions. 
   
   
       9 . The device of  claim 1 , wherein the upstream data handler is a USB high-speed handler, and each respective downstream data handler is a full/low-speed handler. 
   
   
       10 . The device of  claim 1 , further comprising:
 an upstream physical layer device coupled to the upstream port;   a hub controller coupled between the upstream physical layer device and the upstream data handler; and   a plurality of downstream physical layer devices coupled between the plurality of downstream data handlers and the plurality of downstream ports.   
   
   
       11 . A method, comprising:
 a plurality of downstream ports of a USB (Universal Serial Bus) hub operating at a different transfer rate than an upstream port of the USB hub;   an upstream handler associated with the upstream port accepting through the upstream port, at the first data rate, specific transactions comprising data, and storing the specific transactions;   each respective downstream handler of a plurality of downstream handlers accessing respective transactions of the stored specific transactions, wherein each respective downstream handler is associated with a respective downstream port of the plurality of downstream ports, and wherein the respective transactions are intended for the respective downstream port; and   each respective downstream handler transmitting to its associated respective downstream port, at the different data transfer rate, the data comprised in its respective transactions.   
   
   
       12 . The method of  claim 11 , wherein said storing the specific transactions comprises storing the specific transactions in a plurality of memory devices; and wherein each of the plurality of memory devices is associated with a respective downstream handler. 
   
   
       13 . The method of  claim 11 , wherein said storing the specific transactions comprises storing the specific transactions in a shared memory device, the method further comprising:
 each respective downstream handler retrieving the data comprised in its respective transactions from the shared memory device.   
   
   
       14 . The method of  claim 13 , wherein said each respective downstream handler transmitting to its associated respective downstream port includes the plurality of downstream data handlers transmitting to their associated respective ones of the plurality of downstream ports simultaneously. 
   
   
       15 . A system, comprising:
 a shared memory device;   a faster handler configured to store in the shared memory device specific transactions intended for a plurality of slower ports and received through a faster port;   a plurality of slower handlers each coupled to the shared memory device to access respective ones of the stored specific transactions, and transfer data comprised in the respective ones of the stored specific transactions to a respective one of the plurality of slower ports, wherein the plurality of slower ports have respective lower data transfer rates than the faster port;   wherein the faster handler and each of at least two of the slower handlers are conjunctively operable to use the shared memory device to convert from one respective data transfer rate to another respective data transfer rate; and   wherein the faster handler and the plurality of slower handlers are configured to implement a USB (Universal Serial Bus) protocol.   
   
   
       16 . The system of  claim 15 , wherein the faster handler includes at least two buffers, wherein the faster handler is configured to transfer data between the faster port and one of the at least two buffers while also transferring data between the shared memory device and a different one of the at least two buffers. 
   
   
       17 . The system of  claim 16 , wherein a capacity of each of the at least two buffers is equal to an amount of data accessible in the shared memory device in response to a single request initiated by the faster handler. 
   
   
       18 . The system of  claim 15 , further comprising:
 a memory arbiter coupled to the shared memory device, the faster handler, and the plurality of slower handlers and configured to arbitrate between requests to access the shared memory device generated by the faster handler and the plurality of slower handlers.   
   
   
       19 . The system of  claim 18 , wherein the memory arbiter is configured to allow the faster handler to access the shared memory device more frequently than any of the plurality of slower handlers access the shared memory device. 
   
   
       20 . The system of  claim 18 , wherein the memory arbiter is configured to allow the faster handler to access the shared memory device at least every other arbitration cycle in the memory arbiter. 
   
   
       21 . The system of  claim 18 , wherein there are N slower handlers in the plurality of slower handlers, and wherein the memory arbiter is configured to allow one of the plurality of slower handlers to access the shared memory device at least every 2N arbitration cycles in the memory arbiter, wherein N is a positive integer. 
   
   
       22 . The system of  claim 18 , wherein the memory arbiter is configured to arbitrate between the plurality of slower handlers on a round-robin basis. 
   
   
       23 . The system of  claim 18 , wherein the memory arbiter is configured to map data written by the faster handler into a region of the shared memory device corresponding to one of the plurality of slower handlers to which the data is being transferred. 
   
   
       24 . The system of  claim 18 , wherein the memory arbiter is configured to map data written by one of the plurality of slower handlers into a region of the shared memory device corresponding to that one of the slower handlers. 
   
   
       25 . The system of  claim 15 , wherein the shared memory device is a single-ported memory device. 
   
   
       26 . A method, comprising:
 a plurality of ports in a USB (Universal Serial Bus) hub each receiving a respective data stream, wherein at least one of the plurality of ports receives its respective data stream at a different rate than other ones of the plurality of ports, wherein a respective one of a plurality of handlers is associated with each of the plurality of ports, wherein the plurality of handlers are configured to implement a USB protocol;   arbitrating between the plurality of handlers for access to a shared memory device;   a first handler, associated with a port of the at least one of the plurality of ports, storing, in response to being selected by said arbitrating, to the shared memory device specific transactions included in the respective data stream received by the port of the at least one of the plurality of ports;   each of at least two handlers associated with respective ports of the other ones of the plurality of ports accessing the specific transactions and transmitting data comprised in the specific transactions to the respective ports of the other ones of the plurality of ports; and   wherein the first handler and each of the at least two handlers associated with respective ports of the other ones of the plurality of ports are conjunctively operable to convert from one respective data transfer rate to another respective data transfer rate.   
   
   
       27 . The method of  claim 26 , wherein the first handler is a faster handler and the port of the at least one of the plurality of ports is a faster port of the plurality of ports, wherein the faster handler includes at least two buffers, wherein the faster handler is configured to transfer data between the faster port and one of the at least two buffers while also transferring data between the shared memory device and a different one of the at least two buffers. 
   
   
       28 . The method of  claim 27 , wherein a capacity of each of the at least two buffers is equal to an amount of data accessible in the shared memory device in response to a single request initiated by the faster handler. 
   
   
       29 . The method of  claim 26 , wherein the first handler is a faster handler associated with a faster port of the plurality of ports, wherein said arbitrating allows the faster handler to access the shared memory device more frequently than any other handlers of the plurality of handlers. 
   
   
       30 . The method of  claim 26 , wherein the shared memory device is a single-ported memory device. 
   
   
       31 . The method of  claim 26 , wherein the specific transactions are high-speed split transactions.