Vector processing system

Abstract

A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

1 - 20 . (canceled) 
   
   
       21 . An integrated circuit comprising:
 a first circuit operable to perform an operation on a plurality of value pairs to generate a respective plurality of intermediate outputs, wherein the plurality of intermediate outputs are generated during the same or substantially the same period of time, and wherein each intermediate output is identified by an index; and   a second circuit operable to receive the plurality of intermediate outputs and return the index of one intermediate output according to a predefined condition.   
   
   
       22 . The integrated circuit according to  claim 21 , wherein the operation, the plurality of value pairs, and the predefined condition are defined by an instruction. 
   
   
       23 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to return the value of one intermediate output according to the predefined condition. 
   
   
       24 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to sum the intermediate outputs. 
   
   
       25 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to return the minimum intermediate output. 
   
   
       26 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to return the maximum intermediate output. 
   
   
       27 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to return the index of the minimum intermediate output. 
   
   
       28 . The integrated circuit according to  claim 21 , wherein the second circuit is operable to return the index of the maximum intermediate output. 
   
   
       29 . The integrated circuit according to  claim 21 , wherein the number of value pairs processed by the first circuit is selectable. 
   
   
       30 . The integrated circuit according to  claim 29 , wherein the second circuit processes the intermediate outputs of processed value pairs. 
   
   
       31 . The integrated circuit according to  claim 21 , wherein the integrated circuit further comprises a memory that holds the plurality of value pairs as packed operands.