Duty cycle detecting circuit for pulse width modulation

Abstract

A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal.

1 . A duty cycle detecting circuit for pulse width modulation, applied for detecting a duty cycle of a PWM signal, comprising:
 a clock generating circuit, for generating a clock signal;   a sampling circuit, for receiving the PWM signal and the clock signal, and sampling the PWM signal based on the clock signal to generate a sampling signal; and   a calculation circuit, for calculating the duty cycle of the PWM signal based on the sampling signal.   
   
   
       2 . The duty cycle detecting circuit for pulse width modulation of  claim 1 , wherein the sampling signal comprises a high electric potential state and a low electric potential state. 
   
   
       3 . The duty cycle detecting circuit for pulse width modulation of  claim 2 , wherein the calculation circuit accumulates the sampling signal into a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively. 
   
   
       4 . The duty cycle detecting circuit for pulse width modulation of  claim 3 , wherein the calculation circuit divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle. 
   
   
       5 . The duty cycle detecting circuit for pulse width modulation of  claim 2 , wherein the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively. 
   
   
       6 . The duty cycle detecting circuit for pulse width modulation of  claim 5 , wherein the calculation circuit divides the count of high electric potential states by a sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. 
   
   
       7 . The duty cycle detecting circuit for pulse width modulation of  claim 1 , wherein the clock generating circuit is an oscillator. 
   
   
       8 . The duty cycle detecting circuit for pulse width modulation of  claim 1 , wherein the calculation circuit comprises:
 a microprocessor unit, for processing an operation required to calculate the duty cycle; and   a memory unit, for storing a computer code required to calculate the duty cycle.   
   
   
       9 . The duty cycle detecting circuit for pulse width modulation of  claim 1 , wherein the sampling circuit is a flip-flop. 
   
   
       10 . The duty cycle detecting circuit for pulse width modulation of  claim 9 , wherein the calculation circuit comprises a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential state to obtain a count of high electric potential states and a count of low electric potential states respectively. 
   
   
       11 . The duty cycle detecting circuit for pulse width modulation of  claim 10 , wherein the calculation circuit further comprises a divider for dividing the count of high electric potential states by a sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. 
   
   
       12 . The duty cycle detecting circuit for pulse width modulation of  claim 10  or  11 , wherein the calculation circuit further comprises a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again. 
   
   
       13 . The duty cycle detecting circuit for pulse width modulation of  claim 9 , wherein the calculation circuit further includes a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively. 
   
   
       14 . The duty cycle detecting circuit for pulse width modulation of  claim 13 , wherein the calculation circuit further comprises a divider for dividing the count of high electric potential states by the total number of times of sampling to obtain the duty cycle. 
   
   
       15 . The duty cycle detecting circuit for pulse width modulation of  claim 13  or  14 , wherein the calculation circuit further comprises a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.