US2009108310A1PendingUtilityA1

CMOS image sensor and fabricating method thereof

52
Assignee: SEO DONG HEEPriority: Dec 30, 2004Filed: Oct 3, 2008Published: Apr 30, 2009
Est. expiryDec 30, 2024(expired)· nominal 20-yr term from priority
H10F 39/8063H10F 39/8053H10F 39/807H10F 39/024H10F 39/18H10F 39/014
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, an insulating interlayer on a plurality of the inner microlenses, a plurality of metal lines within the insulating interlayer, a device protecting layer on the insulating interlayer, and a plurality of microlenses on the device protecting layer.

Claims

exact text as granted — not AI-modified
1 . A CMOS image sensor comprising:
 a plurality of photodiodes on a semiconductor substrate;   a plurality of inner microlenses on a plurality of the photodiodes;   an insulating interlayer on a plurality of the inner microlenses;   a plurality of metal lines within the insulating interlayer;   a device protecting layer on the insulating interlayer; and   a plurality of microlenses on the device protecting layer.   
   
   
       2 . The CMOS image sensor of  claim 1 , wherein a plurality of the inner microlenses are provided within the semiconductor substrate to correspond to a plurality of the photodiodes, respectively. 
   
   
       3 . The CMOS image sensor of  claim 2 , wherein the semiconductor substrate is formed of silicon having an inverse triangle type profile due to an etched degree that varies according to a crystalline direction when etched using an etchant. 
   
   
       4 . The CMOS image sensor of  claim 3 , wherein the semiconductor substrate comprises silicon having a crystalline structure of (1,0,0). 
   
   
       5 . A CMOS image sensor comprising:
 a plurality of photodiodes on a semiconductor substrate;   a first insulating interlayer on a plurality of the photodiodes;   a first metal line within the first insulating interlayer;   a plurality of inner microlenses on the first insulating interlayer;   a second insulating interlayer on a plurality of the inner microlenses;   a second metal line within the second insulating interlayer;   a device protecting layer on the second insulating interlayer; and   a plurality of microlenses on the device protecting layer.   
   
   
       6 . The CMOS image sensor of  claim 5 , further comprising a silicon layer attached to the first insulating interlayer, wherein a plurality of the inner microlenses are formed within the silicon layer to correspond to a plurality of the photodiodes, respectively. 
   
   
       7 . The CMOS image sensor of  claim 6 , wherein the silicon layer is formed of silicon having an inverse triangle type profile due to an etched degree that varies according to a crystalline direction when etched using an etchant. 
   
   
       8 . The CMOS image sensor of  claim 7 , wherein the semiconductor substrate comprises silicon having a crystalline structure of (1,0,0). 
   
   
       9 . A method of fabricating CMOS image sensor, comprising:
 forming a plurality of photodiodes on a semiconductor substrate;   forming a plurality of inner microlenses on a plurality of the photodiodes;   alternately forming insulating interlayers and metal lines on a plurality of the inner microlenses to thereby form the insulating interlayer on the metal line;   forming a device protecting layer on the insulating interlayer; and   forming a plurality of microlenses on the device protecting layer.   
   
   
       10 . The method of  claim 9 , wherein forming a plurality of inner microlenses comprises:
 forming a photoresist pattern on the semiconductor substrate to expose an area corresponding to a plurality of the photodiodes;   forming concave recesses by wet etching performed on the semiconductor substrate using the photoresist pattern as a mask; and   forming a nitride layer on the semiconductor substrate including the concave recesses.   
   
   
       11 . The method of  claim 10 , the concave recesses forming step comprising:
 generating an inverse triangle type profile by performing the wet etching on the semiconductor substrate; and   rounding the inverse triangle type profile by chemical dry etching to form each of the concave recesses.   
   
   
       12 - 14 . (canceled)

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.