Ram with independent local clock

Abstract

In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion of an external clock; a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock independently of whether the external clock has been de-asserted.

1 . A random access memory (RAM), comprising;
 an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines;   a local clock source that asserts a local clock signal in response to an assertion of an external clock signal;   a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address and the assertion of the local clock signal, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and   a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock signal independently of whether the external clock signal has been de-asserted.   
   
   
       2 . The RAM of  claim 1 , wherein the local clock source comprises a plurality of local clock sources corresponding to the plurality of x-decoders such that each x-decoder responds to an assertion of the local clock from its corresponding local clock source. 
   
   
       3 . The RAM of  claim 2 , wherein the array of memory cells are arranged into blocks, the RAM further comprising a controller that decodes an address to determine a block that is selected by the address, the controller controlling the clock sources such that only the local clock sources in the selected block respond to the assertion of the external clock signal. 
   
   
       4 . The RAM of  claim 1 , wherein the assertion of the local clock signal corresponds to a rising edge in the external clock signal. 
   
   
       5 . The RAM of  claim 1 , wherein the assertion of the local clock signal corresponds to a falling edge in the external clock signal. 
   
   
       6 . The RAM of  claim 1 , wherein each x-decoder includes a bit line replica circuit that replicates a delay period between the assertion of the corresponding word line and the voltage development on the bit lines by asserting a bit line completion signal, each bit line replica circuit responding to the assertion of the local clock by asserting the bit line completion signal after the delay period has expired, and wherein the local clock source is de-asserted by a delayed version of the bit line completion signal. 
   
   
       7 . The RAM of  claim 6 , wherein the delayed version of the bit line completion signal comprises a sense command signal, each bit line replica circuit including a driver to assert the sense command signal in response to the assertion of the bit line completion signal, the sense command signal triggering a sense operation by a corresponding one or more of the sense amplifiers, the driver delaying the assertion of the sense command signal according to a delay period between the assertion of the external clock and the assertion of the corresponding word line. 
   
   
       8 . The RAM of  claim 7 , wherein the RAM is a static RAM (SRAM), and wherein each sense amplifier includes a detector that is isolated from the bit lines during a write operation, and wherein the bit line replica circuit comprise read operation bit line replica circuits and write operation bit line replica circuits. 
   
   
       9 . A random access memory (RAM), comprising
 a plurality of arrays of memory cells,   a plurality of local clock sources corresponding to the plurality of arrays, each local clock source adapted to assert a local clock signal; and   a controller adapted to receive read or write operation instructions, the controller selecting which array should respond to a read or write operation instruction by commanding the corresponding local clock source to assert its local clock.   
   
   
       10 . The RAM of  claim 9 , wherein the read or write operation instructions occur according to an assertion of an external clock, the external clock signal cycling at a rate such that a first one of the arrays responds to a first read or write operation instruction while a second one of the arrays is responding to a second read or write operation instruction, the controller thereby demultiplexing the read or write operation instructions among the plurality of arrays. 
   
   
       11 . The RAM of  claim 10 , wherein each array of memory cells is arranged into arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines, and wherein each array further includes:
 a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address and the assertion of the corresponding local clock signal, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and   a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock signal independently of whether the external clock signal has been de-asserted.   
   
   
       12 . The RAM of  claim 11 , wherein the assertion of the local clock signal in a selected array corresponds to a rising edge in the external clock signal. 
   
   
       13 . The RAM of  claim 11 , wherein the assertion of the local clock signal in a selected array corresponds to a falling edge in the external clock signal. 
   
   
       14 . The RAM of  claim 11 , wherein each x-decoder includes a bit line replica circuit that replicates a delay period between the assertion of the corresponding word line and the voltage development on the bit lines in its array by asserting a bit line completion signal, each bit line replica circuit responding to the assertion of the corresponding local clock by asserting the bit line completion signal after the delay period has expired, and wherein the corresponding local clock source is de-asserted by a delayed version of the bit line completion signal. 
   
   
       15 . The RAM of  claim 14 , wherein the delayed version of the bit line completion signal comprises a sense command signal, each bit line replica circuit including a driver to assert the sense command signal in response to the assertion of the bit line completion signal, the sense command signal triggering a sense operation by a corresponding one or more of the sense amplifiers, the driver delaying the assertion of the sense command signal according to a delay period between the assertion of the external clock and the assertion of the corresponding word line. 
   
   
       16 . A method of random access memory (RAM) operation, the method comprising:
 responding to an external clock signal edge by asserting a local clock signal;   in response to the assertion of the local clock, mimicking a first delay period between an assertion of a word line and a resulting voltage development on a word line;   after an expiration of the mimicked first delay period, asserting a bit line completion signal;   in response to the assertion of the bit line completion signal, mimicking a second delay period between a receipt of the read or write operation instruction and the assertion of the word line;   after the expiration of the mimicked second delay period, de-asserting the local clock, whereby the local clock is de-asserted independently of the external clock signal.   
   
   
       17 . The method of  claim 16 , further comprising: after the expiration of the mimicked second delay period, triggering a sense amplifier operation. 
   
   
       18 . The method of  claim 16 , wherein the external clock signal edge is a rising edge. 
   
   
       19 . The method of  claim 16 , wherein the external clock signal edge is a falling edge.