Vertically Aligned Mode Liquid Crystal Display

Abstract

A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

1 . A method of manufacturing a thin film transistor panel comprising:
 forming a gate wire including a plurality of gate lines, a plurality of gate electrodes connected to the gate lines and a plurality of gate pads connected to the gate lines on an insulating substrate;   forming a gate insulating layer;   forming a semiconductor layer;   forming a data wire including a plurality of data line intersecting the gate lines, a plurality of data pads connected to the data lines, a plurality of source electrodes adjacent to gate electrodes a plurality of drain electrodes disposed opposite the source electrodes by depositing and pattering a conductive material;   forming a passivation layer;   forming a plurality of contact holes exposing the gate pads, the data pads and the drain electrodes by patterning the passivation layer together with the gate insulating layer; and   forming a plurality of auxiliary gate pads, a plurality of auxiliary data pads and a plurality of pixel electrodes respectively connected to the gate pads, the data pads and the drain electrodes via the contact holes by depositing and patterning a transparent conductive layer,   wherein the formation of a plurality of pixel electrodes makes adjacent two of the pixel electrodes opposite each other with respect to one of the data lines to have a substantial inversion symmetry.   
   
   
       2 . The method of  claim 1 , wherein the data wire and the semiconductor layer are formed together by one photolithography using a photoresist pattern having a first portion, a second portion thinner than the first portion, and a third portion thinner than the second portion. 
   
   
       3 . The method of claim of  2 , wherein the second portion is located between one of the source electrodes and one of the drain electrodes and the first portion is located on the data wire in the one photolithography.