Method for patterning mo layer in a photovoltaic device comprising cigs material using an etch process

Abstract

A processing method described herein provides a method of patterning a MoSe 2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe 2 . According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe 2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe 2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.

1 . A method of processing a thin-film structure comprising:
 etching completely through a portion of a thin film layer in the thin-film structure, wherein the thin film layer comprises molybdenum, thereby completely exposing a corresponding underlying portion of the thin-film structure that does not comprise molybdenum.   
   
   
       2 . A method according to  claim 1 , wherein the etched thin film layer further comprises selenium. 
   
   
       3 . A method according to  claim 1 , wherein the etched thin film layer comprises Mo and MoSe 2 . 
   
   
       4 . A method according to  claim 1 , further including defining a masking layer so as to pattern the thin film layer and thereby define the etched portion of the thin film layer. 
   
   
       5 . A method according to  claim 1 , wherein the etching step includes using a wet etch chemistry. 
   
   
       6 . A method according to  claim 1 , wherein the etching step includes using a dry etch chemistry. 
   
   
       7 . A method according to  claim 5 , wherein the etched thin film layer comprises a conducting film in a solar cell stack. 
   
   
       8 . A method according to  claim 5 , wherein the thin-film structure further comprises a different layer comprising CIGS film. 
   
   
       9 . A method according to  claim 5 , wherein the thin-film structure further comprises a different layer comprising CdTe. 
   
   
       10 . A method according to  claim 5 , wherein the thin-film structure further comprises a different layer comprising amorphous silicon. 
   
   
       11 . A method according to  claim 5 , wherein the thin-film structure further comprises a different layer comprising micro- or nano-crystal silicon. 
   
   
       12 . A method according to  claim 5 , wherein the wet etch chemistry includes NaClO. 
   
   
       13 . A method according to  claim 1 , wherein an etch rate is in excess of 5 Å/sec. 
   
   
       14 . A method according to  claim 1 , wherein the thin-film structure further comprises a photovoltaic film layer, and wherein an etch rate at which the etching removes the thin film layer is at least 5 times greater than an etch rate at which the etching removes the photovoltaic film layer. 
   
   
       15 . A method according to  claim 14 , wherein the photovoltaic film comprises CIGS. 
   
   
       16 . A method according to  claim 4 , wherein the step of defining the masking layer includes depositing a photoresist layer and using photolithography to create a pattern, and wherein an etch rate at which the etching removes the thin film layer is at least 5 times greater than an etch rate at which the etching removes the photoresist layer. 
   
   
       17 . A method according to  claim 1 , wherein the etching step further includes forming test structures in the thin film structure. 
   
   
       18 . A method according to  claim 17 , wherein intermediate layers in the thin-film structure are removed so that the test structures are formed on a base that includes fewer layers than the entire thin-film structure at the point in the process. 
   
   
       19 . A method according to  claim 17 , wherein the test structures are electrically isolated from an actual device formed in the thin-film structure.