Display control device and mobile electronic apparatus

Abstract

A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc.

1 - 40 . (canceled) 
     
     
         41 . A display control device formed on a semiconductor substrate, comprising:
 a memory which is capable of storing display data to be displayed on a display device;   a driver circuit which drives the display device in accordance with the display data that is read from the memory;   a plurality of external terminals which are supplied the display data to be stored to the memory supplied from outside of the display control device;   a first data holding circuit which is capable of holding the display data by taking the display data supplied from outside of the display control device in units of a predetermined number of bits; and   a second data holding circuit which is capable of holding the display data by receiving the display data supplied from the first data holding circuit in units of n times said predetermined number of bits, where n is an integer larger than 1,   wherein the display data output from the second data holding circuit in units of n times said predetermined number of bits is written to the memory in parallel with a next display data, that follows the display data, supplied from outside of the display control device in units of a predetermined number of bits, and is received from the first data holding circuit.   
     
     
         42 . A display control device according to  claim 41 ,
 wherein the display data is for animated display.   
     
     
         43 . A display control device according to  claim 41 ,
 wherein the display data is for color display including red, green and blue data.   
     
     
         44 . A display control device according to  claim 41 , further including:
 a first driver which generates a drive signal to be supplied to the display device.   
     
     
         45 . A display control device according to  claim 41 , further including:
 a gradation voltage generation circuit; and   a gradation voltage select circuit which selects a desired gradation voltage suitable for the display data that is read from the memory, the gradation voltage being generated by the gradation voltage generation circuit.   
     
     
         46 . A display control device according to  claim 41 ,
 wherein the memory stores the display data in a bit map system.   
     
     
         47 . A display control device according to  claim 41 ,
 wherein the first data holding circuit includes a plurality of latch circuits, wherein the number of latch circuits is equal to a number of memory cells coupled to one word line of the memory.   
     
     
         48 . A display control device according to  claim 41 ,
 wherein the display data is supplied to the first data holding circuit via the external terminals.   
     
     
         49 . A display control device according to  claim 48 ,
 wherein the number of external terminals is the same as said predetermined number of bits.   
     
     
         50 . A display control device according to  claim 41 ,
 wherein the units of predetermined number of bits is units of 16 bits, and   wherein the units of n times said predetermined number of bits, where n is an integer larger than 1, is units of 64 bits.   
     
     
         51 . A display control device according to  claim 41 ,
 wherein the display data of said units of n times said predetermined number of bits includes dummy data to be written to the memory.   
     
     
         52 . A display control device according to  claim 41 ,
 wherein the display control device formed on one semiconductor substrate includes a bit operation circuit which performs logical operations for the display data, and   wherein the bit operation circuit is coupled to the first data holding circuit.   
     
     
         53 . A display control device according to  claim 41 ,
 wherein the display control device formed on one semiconductor substrate includes a bit operation circuit which performs logical operations for the display data, and a third data holding circuit which holds the display data read from the memory, and   wherein the bit operation circuit is coupled to the first data holding circuit.   
     
     
         54 . A display control device according to  claim 41 ,
 wherein the display control device formed on one semiconductor substrate includes an address counter which generates addresses for the memory.   
     
     
         55 . A display control device according to  claim 52 ,
 wherein the display control device formed on one semiconductor substrate includes a clock generating circuit which generates clock pulses, and a timing generator which is coupled to the clock generating circuit.   
     
     
         56 . A display control device according to  claim 41 ,
 wherein n is 4.   
     
     
         57 . A liquid crystal display control device formed on one semiconductor substrate, comprising:
 a memory which stores display data to be displayed using a color display liquid crystal panel;   a plurality of first external terminals which are supplied the display data to be stored to the memory supplied from outside of the liquid crystal display control device;   a gradation voltage generation circuit;   a gradation voltage select circuit which selects a gradation voltage from a plurality of gradation voltages generated by the gradation voltage generation circuit, for driving each of a plurality of display picture elements for one line of the color display liquid crystal panel, based on the display data read from the memory;   a first driver which generates drive signals to be supplied to the color display liquid crystal panel based on the gradation voltage selected by the gradation voltage select circuit;   a plurality of second external terminals to which is supplied outputs of the first driver;   a second driver which selects a selection signal for selecting one line to be display from a plurality of lines on the color display liquid crystal panel;   a first data holding circuit which is coupled between the first external terminals and the memory, and which is capable of holding the display data by taking the display data supplied from outside of the display control device in units of a number of bits suitable for the number of the first external terminals, and which is capable of supplying the display data to the memory in units of n times the number of bits suitable for a number of the first external terminals, where n is an integer larger than 1; and   a second data holding circuit which is capable of holding the display data by taking the display data supplied from the first data holding circuit in units of n times the number of bits suitable for the number of the first external terminals, where n is an integer larger than 1,   wherein the first data holding circuit holds a next display data that follows data of the display data, supplied from outside of the liquid crystal display control device in the units of a number of bits suitable for the number of the first external terminals in parallel with the display data output from the second data holding circuit in units of n times said predetermined number of bits, where n is an integer larger than 1, and that is written to the memory.   
     
     
         58 . A liquid crystal display control device formed on one semiconductor substrate according to  claim 57 , further comprising:
 a third data holding circuit which holds the display data read from the memory.   
     
     
         59 . A liquid crystal display control device according to  claim 57 ,
 wherein the display data is for animated display.   
     
     
         60 . A liquid crystal display control device according to  claim 57 ,
 wherein the display data is for color display including red, green and blue data.   
     
     
         61 . A liquid crystal display control device according to  claim 57 , wherein n is 4. 
     
     
         62 . A liquid crystal display control device according to  claim 57 ,
 wherein the units of the number of bits suitable for the number of the first external terminals is units of 16 bits, and   wherein the units of n times the number of bits suitable for the number of the first external terminals, where n is an integer larger than 1, is units of 64 bits.   
     
     
         63 . A liquid crystal display control device according to  claim 57 ,
 wherein the memory stores the display data in a bit map system.   
     
     
         64 . A liquid crystal display control device according to  claim 57 ,
 wherein the first data holding circuit includes a plurality of latch circuits, wherein the number of the latch circuits is equal to a number of memory cells coupled to one word line of the memory.   
     
     
         65 . A liquid crystal display control device according to  claim 57 ,
 wherein the liquid crystal display control device formed on one semiconductor substrate includes an address counter which generates addresses for the memory.   
     
     
         66 . A liquid crystal display control device according to  claim 57 ,
 wherein the liquid crystal display control device formed on one semiconductor substrate includes a clock generating circuit which generates clock pulses, and a timing generator which is coupled to the clock generating circuit.   
     
     
         67 . A display control device formed on one semiconductor substrate, comprising:
 a memory which is capable of storing display data to be displayed to a display device;   an address counter which generates addresses for the memory;   a driver which drives the display device in accordance with the display data that is read from the memory;   a plurality of external terminals which are supplied the display data to be stored to the memory supplied from outside of the display control device;   a first data holding circuit which is capable of holding the display data by taking the display data supplied from outside of the display control device in units of the predetermined number of bits; and   a second data holding circuit which is capable of holding the display data by taking the supply data supplied from the first data holding circuit in units of n times the predetermined number of bits, where n is an integer larger than 1,   wherein the display data output from the second data holding circuit in units of n times the predetermined number of bits, where n is an integer larger than 1, is written to the memory in parallel with a next display data that follows the display data supplied from outside of the display control device in units of the predetermined number of bits from the first data holding circuit.   
     
     
         68 . A display control device according to  claim 67 ,
 wherein the display data is for animated display.   
     
     
         69 . A display control device according to  claim 67 ,
 wherein the display data is for color display including red, green and blue data.   
     
     
         70 . A display control device according to  claim 67 ,
 a gradation voltage generation circuit; and   a gradation voltage select circuit which selects a desired gradation voltage suitable for the display data that is read from the memory, the gradation voltage being generated by the gradation voltage generation circuit.   
     
     
         71 . A display control device according to  claim 67 ,
 wherein the memory stores the display data in a bit map system.   
     
     
         72 . A display control device according to  claim 67 ,
 wherein the first data holding circuit includes a plurality of latch circuits, wherein the number of latch circuits is equal to a number of memory cells coupled to one word line of the memory.   
     
     
         73 . A display control device according to  claim 67 ,
 wherein the display data is supplied to the first data holding circuit via said external terminals.   
     
     
         74 . A display control device according to  claim 73 ,
 wherein the number of said external terminals is the same as the predetermined number of bits.   
     
     
         75 . A display control device according to  claim 67 ,
 wherein the units of the predetermined number of bits is units of 16 bits, and   wherein the units of n times said predetermined number of bits, where n is an integer and n is larger than 1, is units of 64 bits.   
     
     
         76 . A display control device according to  claim 67 ,
 wherein the display data of said units of n times said predetermined number of bits includes dummy data to be written to the memory.   
     
     
         77 . A display control device according to  claim 67 ,
 wherein the display control device formed on one semiconductor substrate includes a bit operation circuit which performs logical operations for the display data, and   wherein the bit operation circuit is coupled to the first data holding circuit.   
     
     
         78 . A display control device according to  claim 67 ,
 wherein the display control device formed on one semiconductor substrate includes a bit operation circuit which performs logical operations for the display data, and a third data holding circuit which holds the display data read from the memory, and   wherein the bit operation circuit is coupled to the first data holding circuit.   
     
     
         79 . A display control device according to  claim 67 ,
 wherein the display control device formed on one semiconductor substrate includes a clock generating circuit which generates clock pulses, and a timing generator which is coupled to the clock generating circuit.