Maintaining Circuit Delay Characteristics During Power Management Mode

Abstract

A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.

1 . An apparatus for maintaining circuit characteristics comprising
 a selector circuit, the selector circuit receiving a clock signal, a power saving clock signal and a clock gating signal;   a buffer circuit coupled to the selector circuit, the clock gating signal causing the selector circuit to pass the power saving clock signal to the buffer circuit when the apparatus is operating in a power saving mode of operation, the power saving clock signal continually toggling the buffer circuit at a frequency sufficiently low so at to not impact chip power dissipation while being high enough to minimize asymmetrical stress within the buffer circuit; and,   a receive circuit coupled to the buffer circuit.   
   
   
       2 . The apparatus of  claim 1  wherein
 the buffer circuit comprises a plurality of buffers, each of the plurality of buffers comprising a P-type device and an N-type device; and,   the frequency of the power saving clock signal is high enough to minimize asymmetrical stress on the buffer circuit devices so that electrical characteristics of the P-type device and the N-type device equally change over time.   
   
   
       3 . The apparatus of  claim 1  further comprising:
 a divider receiving the clock signal, the divider generating the power saving clock signal.   
   
   
       4 . The apparatus of  claim 1  wherein:
 a frequency of the power saving clock signal is a small percentage of a frequency of the clock signal.   
   
   
       5 . The apparatus of  claim 1  wherein:
 the clock signal comprises a non-50% duty cycle; and,   the power saving clock signal is distorted to null asymmetrical stress caused by the non-50% duty cycle.   
   
   
       6 . A method for maintaining circuit characteristics comprising
 generating a clock signal, a power saving clock signal and a clock gating signal   selecting one of the clock signal and the power saving clock signal with the clock gating signal to provide a selected clock signal;   providing the selected clock signal to a buffer circuit, the clock gating signal being provided to the buffer circuit to operate the buffer circuit in a power saving mode of operation, the power saving clock signal continually toggling the buffer circuit at a frequency sufficiently low so at to not impact chip power dissipation while being high enough to minimize asymmetrical stress within the buffer circuit.   
   
   
       7 . The method of  claim 6  wherein
 the buffer circuit comprises a plurality of buffers, each of the plurality of buffers comprising a P-type device and an N-type device; and,   the frequency of the power saving clock signal is high enough to minimize asymmetrical stress on the buffer circuit devices so that electrical characteristics of the P-type device and the N-type device equally change over time.   
   
   
       8 . The method of  claim 6  further comprising:
 generating the power saving clock signal by dividing the clock signal.   
   
   
       9 . The method of  claim 6  wherein:
 a frequency of the power saving clock signal is a small percentage of a frequency of the clock signal.   
   
   
       10 . The method of  claim 1  wherein:
 the clock signal comprises a non-50% duty cycle; and,   the power saving clock signal is distorted to null asymmetrical stress caused by the non-50% duty cycle.   
   
   
       11 . A data processing system comprising:
 a clock circuit, the clock circuit comprising
 a selector circuit, the selector circuit receiving a clock signal, a power saving clock signal and a clock gating signal; 
 a buffer circuit coupled to the selector circuit, the clock gating signal causing the selector circuit to pass the power saving clock signal to the buffer circuit when the apparatus is operating in a power saving mode of operation, the power saving clock signal continually toggling the buffer circuit at a frequency sufficiently low so at to not impact chip power dissipation while being high enough to minimize asymmetrical stress within the buffer circuit; and, 
 a receive circuit coupled to the butter circuit. 
   
   
   
       12 . The data processing system of  claim 11  wherein
 the buffer circuit comprises a plurality of buffers, each of the plurality of buffers comprising a P-type device and an N-type device; and,   the frequency of the power saving clock signal is high enough to minimize asymmetrical stress on the buffer circuit devices so that electrical characteristics of the P-type device and the N-type device equally change over time.   
   
   
       13 . The data processing system of  claim 11  further comprising:
 a divider receiving the clock signal, the divider generating the power saving clock signal.   
   
   
       14 . The data processing system of  claim 11  wherein:
 a frequency of the power saving clock signal is a small percentage of a frequency of the clock signal.   
   
   
       15 . The data processing system of  claim 11  wherein:
 the clock signal comprises a non-50% duty cycle; and,   the power saving clock signal is distorted to null asymmetrical stress caused by the non-50% duty cycle.