Enhanced DRAM with Embedded Registers

Abstract

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.

1 - 70 . (canceled) 
     
     
         71 . An integrated circuit comprising:
 a row enable input for receiving a signal indicating that a row address is present at address inputs to the integrated circuit;   a row address latch for storing a row address present at address inputs to the integrated circuit;   an array of DRAM memory cells organized in rows and columns;   a set of sense amplifiers for performing a DRAM row access by accessing the array of DRAM memory cells identified by the stored row address;   a column address input for receiving a signal, during a DRAM row access, indicating that a column address is present at address inputs to the integrated circuit;   a column address latch for storing the column address during a DRAM row access in response to the column address input;   a write enable input for receiving a signal, during a DRAM row access, indicating that data is present at data inputs to the integrated circuit;   a data latch for storing data in response to the write enable input; and   a write signal generator for generating an internal write signal, after completion of the DRAM row access, to store the data in the data latch to the array of DRAM memory cells in a location identified by the column address in the column address latch.   
     
     
         72 . The integrated circuit of  claim 71 , further comprising a set of static registers separate from the set of sense amplifiers, wherein subsets of the static registers are associated with individual rows in the array. 
     
     
         73 . The integrated circuit of  claim 72 , wherein each subset of static registers is arranged as a row and is configured to store at least 32 data bits from the associated subset set of sense amplifiers. 
     
     
         74 . The integrated circuit of  claim 72 , wherein each subset of static registers is arranged as a row and is capable of storing at least 512 data bits from the associated subset set of sense amplifiers. 
     
     
         75 . The integrated circuit of  claim 72 , wherein the array is arranged as a plurality of DRAM subarrays each having a respective plurality of bit lines, the set of static registers is arranged as a plurality of sets of registers corresponding in number to the plurality of DRAM subarrays, each DRAM subarray is coupled to only one respective set of registers, and each set of registers is coupled to receive and store read data from only one corresponding DRAM subarray. 
     
     
         76 . The integrated circuit of  claim 75 , wherein each set of registers is arranged as a row and is capable of storing at least 32 data bits from its the corresponding DRAM subarrays. 
     
     
         77 . The integrated circuit of  claim 76 , wherein each set of registers is arranged as a row and is capable of storing at least 512 data bits from its the corresponding DRAM subarray. 
     
     
         78 . The integrated circuit of  claim 76 , wherein each DRAM subarray is positioned between its respective set of registers and the set of associated sense amplifiers corresponding to the DRAM subarray. 
     
     
         79 . The integrated circuit of  claim 78 , wherein each DRAM subarray is positioned between its respective set of the registers and the set of associated sense amplifiers corresponding to the subarray. 
     
     
         80 . An integrated circuit comprising:
 an output buffer;   a row enable input for receiving a signal indicating that a row address is present at address inputs to the integrated circuit;   a row address latch for storing a row address present at address inputs to the integrated circuit;   an array of DRAM memory cells organized in rows and columns;   a set of sense amplifiers for performing a DRAM row access by accessing the array of DRAM memory cells identified by the stored row address;   a column address input for receiving a signal, during a DRAM row access, indicating that a column address is present at address inputs to the integrated circuit;   a column address latch for storing the column address during a DRAM row access in response to the column address input;   a write enable input for receiving a signal, during a DRAM row access, indicating that data is present at data inputs to the integrated circuit;   a data latch for storing data in response to the write enable input;   a write signal generator for generating a write signal, after completion of the DRAM row access, to store the data in the data latch to the array of DRAM memory cells in a location identified by the column address in the column address latch;   a plurality of read only bit lines selectively coupled to the output buffer; and   a plurality of write only bit lines selectively coupled to the set of sense amplifiers and configured so that all data to be written to the array is written to the sense amplifiers using the write only bit lines and not the read only bit lines.   
     
     
         81 . The integrated circuit of  claim 80 , further comprising a set of static registers separate from the set of sense amplifiers, wherein subsets of the static registers are associated with individual rows in the array; and
 wherein the plurality of read only bit lines are selectively coupled to the set of static registers.   
     
     
         82 . The integrated circuit of  claim 81 , wherein the set of sense amplifiers and the set of static registers are respectively disposed on opposing ends of the array of DRAM memory cells, and
 wherein, in response to a data request including an address that identifies a row in the array that corresponds to a subset of static registers, the read only bit lines being coupled to the corresponding subset of static registers and the write only bit lines being coupled to the corresponding subset of sense amplifiers such that data in the corresponding subset of static registers is output to the output buffer using the subset of sense amplifiers associated with the row identified by the data request address.   
     
     
         83 . The integrated circuit of  claim 82 , wherein each subset of static registers is arranged as a row and is capable of storing at least 32 data bits from the associated subset of sense amplifiers. 
     
     
         84 . The integrated circuit of  claim 83 , wherein each subset of static registers is arranged as a row and is capable of storing at least 512 data bits from the associated subset of sense amplifiers. 
     
     
         85 . The integrated circuit of  claim 81 , wherein the array is arranged as a plurality of DRAM subarrays each having a respective plurality of bit lines;
 wherein the set of static registers is arranged as a plurality of sets of registers corresponding in number to the plurality of DRAM subarrays; and   wherein each the subarray is coupled to only one respective set of the registers, and each set of registers is coupled to receive and store read data from only one corresponding DRAM subarray.   
     
     
         86 . The integrated circuit of  claim 85 , wherein each of the set of static registers is arranged as a row and is capable of storing at least 32 data bits from its the corresponding DRAM subarrays. 
     
     
         87 . The integrated circuit of  claim 86 , wherein each the DRAM subarray is positioned between its respective set of the registers and the set of associated sense amplifiers corresponding to the DRAM subarray. 
     
     
         88 . The integrated circuit of  claim 85 , wherein each of the set of static registers is arranged as a row and is capable of storing at least 512 data bits from its the corresponding DRAM subarray. 
     
     
         89 . The integrated circuit of  claim 85 , wherein each the DRAM subarray is positioned between its respective set of the registers and the set of associated sense amplifiers corresponding to the subarray. 
     
     
         90 . An integrated circuit comprising:
 an output buffer;   a row enable input for receiving a signal indicating that a row address is present at address inputs to the integrated circuit;   a row address latch for storing a row address present at address inputs to the integrated circuit;   an array of DRAM memory cells organized in rows and columns;   a set of sense amplifiers for performing a DRAM row access by accessing the array of DRAM memory cells identified by the stored row address;   a column address input for receiving a signal, during a DRAM row access, indicating that a column address is present at address inputs to the integrated circuit;   a column address latch for storing the column address during a DRAM row access in response to the column address input;   a write enable input for receiving a signal, during a DRAM row access, indicating that data is present at data inputs to the integrated circuit;   a data latch for storing data in response to the write enable input;   a write signal generator for generating a write signal, after completion of the DRAM row access, to store the data in the data latch to the array of DRAM memory cells in a location identified by the column address in the column address latch;   a plurality of read only bit lines selectively coupled to the output buffer; and   a decoupling circuit configured to decouple the array from the registers when data is being output from the registers to the output buffer via the read only bit lines; and   a precharging circuit coupled to the decoupling circuit that is configured to precharge the array.   
     
     
         91 . The integrated circuit of  claim 90 , further comprising a set of static registers separate from the set of sense amplifiers, wherein subsets of the static registers are associated with individual rows in the array; and
 wherein the plurality of read only bit lines are selectively coupled to the set of static registers.   
     
     
         92 . The integrated circuit of  claim 91 , wherein, in response to a data request including an address that identifies a row in the array that corresponds to a subset of static registers, the read only bit lines being coupled to the corresponding subset of static registers such that data in the corresponding subset of static registers is output to the output buffer using the subset of sense amplifiers associated with the row identified by the data request address. 
     
     
         93 . The integrated circuit of  claim 91 , further comprising a refresh circuit coupled to the decoupling circuit configured to refresh the array contemporaneously with the data being output from the set of static registers to the output buffer via the read only bit lines.