Inter-Integrated Circuit (12C) Slave with Read/Write Access to Random Access Memory

Abstract

A program and device for data access via an inter-integrated circuit (I2C) protocol are provided, which includes receiving an I2C read command at an I2C slave device from an I2C master device, and the I2C read command at the I2C slave device is altered such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from internal memory of I2C slave device. An I2C write command having master data and a slave device register address is intended to write to the internal memory of the I2C slave device, and I2C write command at the I2C slave device is altered such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to internal memory of the I2C slave device.

1 . A computer program product, tangibly embodied on a computer readable medium, the computer program product including instructions for causing a computer to execute a method for data access via an inter-integrated circuit (I2C) protocol, comprising:
 receiving an I2C read command at an I2C slave device from an I2C master device, the I2C read command being intended to read from an internal memory of the I2C slave device;   in response to receiving the I2C read command to read from the internal memory of the I2C slave device, altering the I2C read command at the I2C slave device such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from the internal memory of the I2C slave device;   wherein:
 the stored data is at a first location in the storage device corresponding to a value in a register array pointer in the I2C slave device; 
 the I2C slave device, the storage device, and an imbedded microprocessor are located on a programmable logic device (PLD); and 
 the storage device and the imbedded microprocessor are separate components than the I2C slave device; 
   receiving an I2C write command at the I2C slave device from the I2C master device, the I2C write command being intended to write to the internal memory of the I2C slave device;   wherein the I2C write command includes master data and a slave device register address; and   in response to receiving the I2C write command to write to the internal memory of the I2C slave device, altering the I2C write command at the I2C slave device such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to the internal memory of the I2C slave device.   
   
   
       2 . The computer program product of  claim 1 , wherein the storage device is volatile. 
   
   
       3 . The computer program product of  claim 1 , wherein the storage device is non-volatile. 
   
   
       4 . The computer program product of  claim 1 , wherein the storage device is a random access memory (RAM) device. 
   
   
       5 . The computer program product of  claim 1 , wherein the I2C slave device is in communication with the I2C master device via a serial data line and a serial clock line. 
   
   
       6 . The computer program product of  claim 1 , wherein the I2C slave device is in communication with the storage device via a memory write signal, a memory read signal, a write enable strobe and a memory address signal. 
   
   
       7 . An I2C slave device comprising:
 a register array pointer containing a current register location value;   a serial data port and serial clock port adapted for receiving commands from an I2C master device;   a plurality of storage device ports adapted for communicating with a storage device; and   a microprocessor including instructions to implement a method including:   receiving an I2C read command at the I2C slave device from an I2C master device, the I2C read command being intended to read from an internal memory of the I2C slave device;   in response to receiving the I2C read command to read from the internal memory of the I2C slave device, altering the I2C read command at the I2C slave device such that the I2C read command causes stored data to be read from the storage device, being external to the I2C slave device, in place of reading from the internal memory of the I2C slave device;   wherein:
 the stored data is at a first location in the storage device corresponding to a value in the register array pointer in the I2C slave device; 
 the I2C slave device, the storage device, and an imbedded microprocessor are located on a programmable logic device (PLD); and 
 the storage device and the imbedded microprocessor are separate components than the I2C slave device; 
   receiving an I2C write command at the I2C slave device from the I2C master device, the I2C write command being intended to write to the internal memory of the I2C slave device;   wherein the I2C write command includes master data and a slave device register address; and   in response to receiving the I2C write command to write to the internal memory of the I2C slave device, altering the I2C write command at the I2C slave device such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to the internal memory of the I2C slave device.   
   
   
       8 . The device of  claim 7 , wherein the storage device is a RAM device. 
   
   
       9 . The device of  claim 7 , wherein the storage device is volatile. 
   
   
       10 . The device of  claim 7 , wherein the storage device is non-volatile. 
   
   
       11 . The device of  claim 7 , wherein the storage device ports include a memory write signal port, a memory read signal port, a write enable strobe port and a memory address signal port.