High performance memory and system organization for digital signal processing

Abstract

An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP operations as loop iterations such that there is maximal reuse of data between multiple consecutive iterations. Independent set up and preparation of data before it is required through suitable mechanisms such as data pre-fetching may be used. This technique may be useful and important for devices that require cost-effective, high-performance, power consumption efficient VLSI IC.

1 - 5 . (canceled) 
   
   
       6 . A digital signal processing technique comprising the steps of:
 matching a computation rate to a rate that data is available;   organizing computation operations into a plurality of loop iterations such that a substantial portion of the data that is available is reused in consecutive ones of the plurality of loop iterations;   fetching the data that is available;   performing at least one of the plurality of loop iterations; and   repeating the steps of fetching the data and performing at least one of the plurality of loop iterations until all the data is processed.   
   
   
       7 . An apparatus for signal processing comprising:
 means for matching computation and data availability rates;   means for organizing computation operations into a plurality of loop iterations such that a substantial portion of the data that is available is reused in consecutive ones of the plurality of loop iterations;   means for fetching data and making the data available for computation;   means for performing at least one of the plurality of loop iterations; and   means for repeating the steps of fetching the data and performing at least one of the plurality of loop iterations until all the data is processed.   
   
   
       8 . The technique of  claim 6 , wherein the step of matching a computation rate to a rate that data is available further comprises:
 determining when the data will be available;   determining when a computed output is required; and   setting a computation rate such that the computation operations begin after the data is available and complete before the computed output is required.   
   
   
       9 . The technique of  claim 8 , wherein the step of determining when the data will be available further comprises:
 signaling when the data is available by performing at least one of:   generating a hardware interrupt signal;   setting a flag; and   generating a software semaphore signal.   
   
   
       10 . The technique of  claim 6 , wherein the step of organizing computation operations into a plurality of loop iterations further comprises:
 selecting an ordered scanning pattern through the data; and   selecting the plurality of loop iterations to correspond to the ordered scanning pattern such that reuse of the data in consecutive ones of the plurality of loop iterations is substantially maximized.   
   
   
       11 . The technique of  claim 6 , wherein the step of fetching the data that is available further comprises:
 selecting an ordered scanning pattern through the data;   prefetching the data according to the selected ordered scanning pattern; and   making the prefetched data available for the computing operations.   
   
   
       12 . The technique of  claim 11 , wherein the step of prefetching the data further comprises:
 generating an address suitable for addressing an enhanced multi-way data cache that is adapted to store the data; and   reading the data from the enhanced multi-way data cache.   
   
   
       13 . The technique of  claim 6 , wherein the step of performing at least one of the plurality of loop iterations further comprises calculating a video-coding-motion-estimation metric by calculating a pixel-wise difference between suitable portions of the data that is available. 
   
   
       14 . The technique of  claim 13 , further comprising compensating for video motion by storing suitable portions of the data that is available when the video-coding-motion-estimation metric indicates movement. 
   
   
       15 . The technique of  claim 6 , wherein the step of performing at least one of the plurality of loop iterations further comprises image filtering by applying a linear function to suitable portions of the data that is available. 
   
   
       16 . The technique of  claim 6 , wherein the step of performing at least one of the plurality of loop iterations further comprises transforming the data that is available in two dimensions by applying a complex function to suitable portions of the data that is available. 
   
   
       17 . The technique of  claim 6 , wherein the step of performing at least one of the plurality of loop iterations further comprises performing a one-dimensional correlation of the data that is available. 
   
   
       18 . The technique of  claim 6 , wherein the step of performing at least one of the plurality of loop iterations further comprises scheduling the at least one of the plurality of loop iterations to occur simultaneously with the step of fetching the data that is available. 
   
   
       19 . The apparatus of  claim 7 , wherein the means for organizing computation operations further comprises:
 a means for determining when the data will be available;   a means for determining when a computed output is required; and   a means for setting a computation rate such that the computation operations begin after the data is available and complete before the computed output is required.   
   
   
       20 . The apparatus of  claim 7 , wherein the means for organizing computation operations comprises a finite state machine. 
   
   
       21 . The apparatus of  claim 7 , wherein the means for organizing computation operations comprises a centralized controller. 
   
   
       22 . The apparatus of  claim 7 , wherein the means for fetching data and making the data available for computation comprises:
 a memory array unit having a control interconnect and a data interconnect; and   a controller adapted to control the memory array unit via the control interconnect and to store and retrieve data via the data interconnect.   
   
   
       23 . The apparatus of  claim 7 , further comprising a means for scheduling the computation operations such that they overlap in time with the function of fetching data and making the data available for computation. 
   
   
       24 . The apparatus of  claim 23 , wherein the means for scheduling the computation operations comprises a finite state machine. 
   
   
       25 . The apparatus of  claim 23 , wherein the means for scheduling the computation operations comprises a centralized controller.