Semiconductor device and method for manufacturing semiconductor device

Abstract

In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

1 . A semiconductor device comprising:
 a substrate including an underlying silicon substrate, a buried insulator, and a semiconductor layer;   a first gate electrode formed on a gate insulator on the semiconductor layer;   a first impurity diffused region formed in a region around an end of the first gate electrode in the longitudinal direction of the first gate electrode in the semiconductor layer by implanting with an impurity of a first conductivity type;   a second impurity diffused region formed in a region in the semiconductor layer in the direction of an extension line of the longitudinal of the first gate electrode by implanting with an impurity of a second conductivity type opposite the first conductivity type;   a first insulator which is formed at least in a region of the semiconductor layer between the second impurity diffused region and the first gate electrode; and   a second gate electrode formed on the first insulator between the second impurity diffused region and the first gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein a portion of the second gate electrode overlaps the second impurity diffused region. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the width of a portion of the first gate electrode in short direction that is on the complete isolation region is wider than the remaining part of the first gate electrode except the other end of the first electrode.
 wherein the first insulator has a complete isolation region on both sides of the width of the first gate electrode at an end of the first gate electrode opposed to the second gate electrode, the complete isolation region penetrating through the semiconductor layer down to the buried insulator.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein the space between the first gate electrode and the second gate electrode on the semiconductor layer is filled with a second insulator. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein a portion of the semiconductor layer between the first gate electrode and the second gate electrode is not implanted with the impurity of the first conductivity type. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein a plurality of the first gate electrodes are formed;
 the first impurity diffused region consists of a plurality of regions separated by the first insulator, each of the plurality of regions is formed around one or more of the plurality of first gate electrodes; and   the second gate electrode is formed between at least one of the first gate electrodes and the second impurity diffused region, the first gate electrode being in at least one of the first impurity diffused regions,   wherein the distance from the first electrode to the second impurity diffused region is long compared to the distance between each of the first electrode and the second impurity diffused region.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein the second gate electrode is provided in such a manner that the second gate electrode surrounds an end of the first gate electrode. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein the space between the second electrode and the first gate electrode is filled with a sidewall. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the space between the second gate electrode and the first gate electrode is further filled with a third insulator.