Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption

Abstract

The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is retrieved from the scratch pad in parallel with a translation of a virtual address to a physical address. If the physical address is associated with the scratch pad, the retrieved instruction is provided to an execution unit. Otherwise, the scratch pad is disabled to reduce power consumption and the instruction fetch is re-initiated. When the scratch pad is disabled, an instruction is retrieved from another instruction source, such as an instruction cache, in parallel with the translation of the virtual address to the physical address. If the physical address is associated with the scratch pad, the scratch pad is enabled and the instruction fetch is re-initiated.

1  A system comprising:
 a processor having a processor core, a fetch unit and a register for storing a portion of an address for an instruction to be fetched;   a first memory source for storing instructions and a scratch pad memory for storing instructions both of which couple to the processor by a bus, wherein the instruction is made available to the processor from the scratch pad memory when the portion of an address stored in the register matches a translated virtual instruction address provided by the fetch unit.   
   
   
       2 . The system of  claim 1  wherein the first memory source is an instruction cache. 
   
   
       3 . The system of  claim 1  wherein the first memory source is a level one instruction cache. 
   
   
       4 . The system of  claim 1  wherein the first memory source is a level two cache. 
   
   
       5 . The system of  claim 1  wherein the first memory source is disabled to reduce power consumption. 
   
   
       6 . The system of  claim 1  wherein the scratch pad memory is disabled to reduce power consumption if the instruction is not made available by the scratch pad memory. 
   
   
       7 . The system of  claim 1  wherein the first memory source is enabled and the scratch pad memory is disabled to reduce power consumption if the instruction is not made available by the scratch pad memory. 
   
   
       8 . The system of  claim 1  wherein the portion of an address for an instruction comprise a tag of the translated physical address of the instruction. 
   
   
       9 . The system of  claim 8  wherein the instruction is selected from scratch pad memory based on the offset of the virtual instruction address. 
   
   
       10 . A method of performing an instruction fetch associated with a virtual address in a processor having a scratch pad memory for storing instructions and a first memory system for storing instructions, comprising:
 making the instruction available to the processor from the scratch pad memory when the portion of an address stored in a register matches a translated virtual instruction address provided by a fetch unit.   
   
   
       11 . The method of  claim 11  wherein the first memory source is an instruction cache. 
   
   
       12 . The method of  claim 10  wherein the first memory source is a level one instruction cache. 
   
   
       13 . The method of  claim 10  wherein the first memory source is a level two cache. 
   
   
       14 . The method of  claim 10  wherein the first memory source is disabled to reduce power consumption. 
   
   
       15 . The method of  claim 10  wherein the scratch pad memory is disabled to reduce power consumption if the instruction is not made available by the scratch pad memory. 
   
   
       16 . The method of  claim 10  wherein the first memory source is enabled and the scratch pad memory is disabled to reduce power consumption if the instruction is not made available by the scratch pad memory. 
   
   
       17 . The method of  claim 10  wherein the portion of the address for an instruction comprises a tag of the translated physical address of the instruction. 
   
   
       18 . The method of  claim 10  wherein the instruction is selected from scratch pad memory based on the offset of the virtual instruction address. 
   
   
       19 . A computer program product for use with a computing device, the computer program product comprising:
 a tangible computer usable medium, having computer readable program code embodied thereon for providing a processor, the computer readable program code comprising:
 first computer readable program code for providing a fetch unit, 
 second computer readable program code for providing a register for storing a portion of an address for an instruction to be fetched, coupled to the fetch unit, 
 third computer readable program code for providing a first memory source for storing instructions, coupled to the fetch unit, and 
 fourth computer readable program code for providing a scratch pad memory for storing instructions, coupled to the fetch unit, 
 wherein the instruction is made available to the processor from the scratch pad memory when the portion of an address stored in the register matches a translated virtual instruction address provided by the fetch unit. 
   
   
   
       20 . The computer program product of  claim 19 , wherein the scratch pad memory is disabled to reduce power consumption if the instruction is not made available by the scratch pad memory.