Calibration of multi-metric sensitive delay measurement circuits

Abstract

A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

1 . A method for determining at least one coefficient relating a delay of a delay circuit to a value of a circuit metric under measurement, the method comprising:
 fixing an environment of the delay circuit so that the circuit metric has a fixed value;   measuring the delay of the delay circuit;   determining from a predetermined relationship expected between the delay of the delay circuit and a position within a process distribution for the circuit, at least one coefficient relating the delay of the delay circuit to the value of the circuit metric; and   storing the at least one coefficient in an electronically-accessible storage location, whereby subsequent delay measurements of the delay circuit are corrected for the process variation using the at least one coefficient.   
   
   
       2 . The method of  claim 1 , wherein the storing stores the at least one coefficient in non-volatile storage located in a die that contains the delay circuit, and wherein the electronically accessible storage location is a location within the non-volatile storage. 
   
   
       3 . The method of  claim 1 , wherein the storing stores the at least one coefficient in a memory of a processor that communicates with an integrated circuit that contains the delay circuit, and wherein the electronically accessible storage location is a location within the memory of the processor. 
   
   
       4 . The method of  claim 1 , wherein the fixing fixes a temperature of the delay circuit, and wherein the method further comprises:
 fixing a voltage of the delay circuit at a first voltage value, wherein the measuring measures the delay for the first voltage value;   fixing the voltage of the delay circuit at a second voltage value;   measuring a second delay corresponding to the second voltage value;   determining a delay difference between the delay and the second delay, and wherein the determining determines, from the delay difference, the position of the delay circuit within a predetermined distribution of delay differences for the particular difference between the first and second voltage; and   determining the at least one coefficient in conformity with the position of the delay circuit within the predetermined distribution of delay differences.   
   
   
       5 . The method of  claim 1 , wherein the delay circuit is a first delay circuit, and wherein the method further comprises second measuring a second time delay of a second delay circuit, wherein a first sensitivity of the time delay of the first delay circuit to the circuit metric under measurement differs from a second sensitivity of a second time delay of the second delay circuit to the circuit metric under measurement, and wherein the determining further determines a second position of the second delay circuit within a second predetermined process distribution for the second delay circuit, and determining at least one second one coefficient relating the time delay of the second circuit to the circuit metric under measurement. 
   
   
       6 . The method of  claim 5 , wherein a third sensitivity of the first time delay of the first circuit to a second circuit metric under measurement differs from a fourth sensitivity of the second time delay of the second circuit to the second circuit metric under measurement, and wherein the method further comprises:
 fixing a value of the second metric prior to the measuring and second measuring; and   determining a third coefficient relating the second time delay of the second circuit to the second circuit metric under measurement.   
   
   
       7 . The method of  claim 6 , further comprising determining a fourth coefficient relating the first time delay of the first circuit to the second circuit metric under measurement. 
   
   
       8 . A test workstation computer system including a memory for storing data and program instructions for determining at least one coefficient relating a delay of a delay circuit to a value of a circuit metric under measurement, a processor for executing the program instructions, and an interface to the delay circuit, wherein the environment of the delay circuit is fixed so that the circuit metric has a fixed value, and wherein the program instructions comprise program instructions for:
 receiving a measured delay of the delay circuit;   determining from a predetermined relationship expected between the delay of the delay circuit and a position within a process distribution for the circuit, at least one coefficient relating the delay of the delay circuit to the value of the circuit metric; and   storing the at least one coefficient in an electronically-accessible storage location, whereby subsequent delay measurements of the delay circuit are corrected for the process variation using the at least one coefficient.   
   
   
       9 . The test workstation computer system of  claim 8 , wherein the program instructions for storing store the at least one coefficient in non-volatile storage located in a die that contains the delay circuit, and wherein the electronically accessible storage location is a location within the non-volatile storage. 
   
   
       10 . The test workstation computer system of  claim 8 , wherein the program instructions for storing store the at least one coefficient in a memory of a processor that communicates with an integrated circuit that contains the delay circuit, and wherein the electronically accessible storage location is a location within the memory of the processor. 
   
   
       11 . The test workstation computer system of  claim 8 , wherein the temperature and supply voltage of the delay circuit are fixed, and wherein the program instructions for determining determine the position of the delay circuit within a predetermined distribution of delays corresponding to the process distribution, and determine the at least one coefficient in conformity with the position of the delay circuit within the predetermined distribution of delay differences. 
   
   
       12 . The test workstation computer system of  claim 8 , wherein the temperature of the delay circuit is fixed, and wherein the program instructions further comprise program instructions for:
 setting a voltage of the delay circuit at a first voltage value, wherein the program instructions for measuring measure the delay for the first voltage value;   setting the voltage of the delay circuit at a second voltage value;   measuring a second delay corresponding to the second voltage value;   determining a delay difference between the delay and the second delay, and wherein the determining determines, from the delay difference, the position of the delay circuit within a predetermined distribution of delay differences for the particular difference between the first and second voltage; and   determining the at least one coefficient in conformity with the position of the delay circuit within the predetermined distribution of delay differences.   
   
   
       13 . The test workstation computer system of  claim 8 , wherein the delay circuit is a first delay circuit, and wherein the program instructions further comprise program instructions for second measuring a second time delay of a second delay circuit, wherein a first sensitivity of the time delay of the first delay circuit to the circuit metric under measurement differs from a second sensitivity of a second time delay of the second delay circuit to the circuit metric under measurement, and wherein the program instructions for determining further determine a second position of the second delay circuit within a second predetermined process distribution for the second delay circuit, and determining at least one second one coefficient relating the time delay of the second circuit to the circuit metric under measurement. 
   
   
       14 . The test workstation computer system of  claim 13 , wherein a third sensitivity of the first time delay of the first circuit to a second circuit metric under measurement differs from a fourth sensitivity of the second time delay of the second circuit to the second circuit metric under measurement, wherein a value of the second metric is fixed prior to executing the program instructions for measuring and second measuring, and wherein the program instructions further comprise program instructions for determining a third coefficient relating the second time delay of the second circuit to the second circuit metric under measurement. 
   
   
       15 . The test workstation computer system of  claim 14 , further comprising program instructions for determining a fourth coefficient relating the first time delay of the first circuit to the second circuit metric under measurement. 
   
   
       16 . A computer program product comprising a computer-readable storage media encoding program instructions for determining at least one coefficient relating a delay of a delay circuit to a value of a circuit metric under measurement, wherein the program instructions comprise program instructions for:
 receiving a measured delay of the delay circuit;   determining from a predetermined relationship expected between the delay of the delay circuit and a position within a process distribution for the circuit, at least one coefficient relating the delay of the delay circuit to the value of the circuit metric; and   storing the at least one coefficient in an electronically-accessible storage location, whereby subsequent delay measurements of the delay circuit are corrected for the process variation using the at least one coefficient.   
   
   
       17 . The computer program product of  claim 16 , wherein the program instructions for storing store the at least one coefficient in non-volatile storage located in a die that contains the delay circuit, and wherein the electronically accessible storage location is a location within the non-volatile storage. 
   
   
       18 . The computer program product of  claim 16 , wherein the program instructions for storing store the at least one coefficient in a memory of a processor that communicates with an integrated circuit that contains the delay circuit, and wherein the electronically accessible storage location is a location within the memory of the processor. 
   
   
       19 . The computer program product of  claim 16 , wherein the temperature and supply voltage of the delay circuit are fixed, and wherein the program instructions for determining determine the position of the delay circuit within a predetermined distribution of delays corresponding to the process distribution, and determine the at least one coefficient in conformity with the position of the delay circuit within the predetermined distribution of delay differences 
   
   
       20 . The computer program product of  claim 16 , wherein the temperature of the delay circuit is fixed, and wherein the program instructions further comprise program instructions for:
 setting a voltage of the delay circuit at a first voltage value, wherein the program instructions for measuring measure the delay for the first voltage value;   setting the voltage of the delay circuit at a second voltage value;   measuring a second delay corresponding to the second voltage value;   determining a delay difference between the delay and the second delay, and wherein the determining determines, from the delay difference, the position of the delay circuit within a predetermined distribution of delay differences for the particular difference between the first and second voltage; and   determining the at least one coefficient in conformity with the position of the delay circuit within the predetermined distribution of delay differences.   
   
   
       21 . The computer program product of  claim 16 , wherein the delay circuit is a first delay circuit, and wherein the program instructions further comprise program instructions for second measuring a second time delay of a second delay circuit, wherein a first sensitivity of the time delay of the first delay circuit to the circuit metric under measurement differs from a second sensitivity of a second time delay of the second delay circuit to the circuit metric under measurement, and wherein the program instructions for determining further determine a second position of the second delay circuit within a second predetermined process distribution for the second delay circuit, and determining at least one second one coefficient relating the time delay of the second circuit to the circuit metric under measurement. 
   
   
       22 . The computer program product of  claim 21 , wherein a third sensitivity of the first time delay of the first circuit to a second circuit metric under measurement differs from a fourth sensitivity of the second time delay of the second circuit to the second circuit metric under measurement, wherein a value of the second metric is fixed prior to executing the program instructions for measuring and second measuring, and wherein the program instructions further comprise program instructions for determining a third coefficient relating the second time delay of the second circuit to the second circuit metric under measurement. 
   
   
       23 . The computer program product of  claim 22 , further comprising program instructions for determining a fourth coefficient relating the first time delay of the first circuit to the second circuit metric under measurement.