Optical driver including a multiphase clock generator having a delay locked loop (dll), optimized for gigahertz frequencies

Abstract

An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks. An optical driver circuit of an optical driving system and a method for implementing a write-strategy for preventing “overlapping” of marks written on adjacent grooves on an optical disc. The circuit and method produce multiple write-strategy waveforms (channels) switching at a high resolution (e.g., T/32) in the Gigahertz frequency range.

1 . A delay locked loop (DLL) circuit comprising:
 a first series of M first delay cells disposed in a feedback loop, each first delay cell providing a delay of N×D, wherein N is an odd integer and D is controlled by a control voltage; and   a second series of M second delay cells, each having a delay of N×D, for generating M clocks having M different phases respectively based on an input clock.   
   
   
       2 . A circuit comprising:
 a delay locked loop (DLL) circuit including a first series of M first delay cells disposed in a feedback loop, each first delay cell providing a delay of N×D, wherein N is an odd integer and D is controlled by a control voltage; and   a second series of M second delay cells, each having a delay of N×D, for generating M clocks having M different phases respectively based on an input clock.   
   
   
       3 . A multiphase clock generator, comprising:
 a first plurality M of voltage-controlled delay elements for incrementally delaying a divided input reference clock signal;   a frequency divider for dividing the frequency of an input reference clock signal by N, and outputting the divided input reference clock signal to the first plurality of voltage-controlled delay elements;   a second plurality M of voltage-controlled delay elements for incrementally delaying the input reference clock signal and for outputting M multi-phase clocks;   a loop filter for generating a control signal voltage to adjust the step delay of each voltage-controlled delay element of the first and second pluralities of voltage-controlled delay elements.