Memory cell circuit, memory device, motion vector detector, and motion compensation predictive encoder

Abstract

The invention relates to a memory device and the like. The memory device comprises one or more memory block. The memory block has a memory cell array consists of multiple memory cells ( 210 ) arranged in a matrix form. A region of the multiple memory cells ( 210 ) includes multiple divisional domains ( 201 a - 201 e ) divided in the direction along word line (WL). Each of the word lines (WL) has multiple divisional selection lines (WLa-WLe) divided corresponding to the multiple divisional domains. The memory block has a switching mechanism ( 220 ) for switching the divisional word lines (Wt) that are to be simultaneously activated in each of the divisional domains. Multiple memory cells ( 210 ) associated with each of the divisional word lines store a horizontal or vertical array of pixel data. The inventive memory device enables simultaneous access to multiple items of pixel data constituting a pixel block having an arbitrary configuration.

1 - 11 . (canceled) 
   
   
       12 . A motion vector detector for detecting a motion vector from a reference frame and a search frame that are displaced in time, comprising:
 a first memory unit for storing multiple items of pixel data constituting said reference frame;   a second memory unit for storing multiple items of pixel data constituting said search frame;   an operation unit for receiving pixel data of the reference block read out of said first memory unit and pixel data of multiple candidate blocks in the search block, said pixel data of multiple candidate blocks being associated with said reference block and read out of said second memory unit, and for calculating differences between the pixel data in said multiple candidate blocks and the pixel data of said reference block every corresponding item of pixel data, in relation to the respective multiple candidate blocks; and   a motion vector detection unit for detecting a motion vector associated with said reference block based on said differences calculated for each of the items of pixel data in relation to the respective multiple candidate blocks operated in said operation unit;   wherein each of said first and second memory units comprises one or more semiconductor memory block;   wherein said semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines; and   multiple memory cells arranged in a matrix form and connected with said bit lines and said word lines;   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line;   wherein each of said multiple selection lines has multiple divisional word lines divided corresponding to said multiple divisional domains; and   wherein said semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in said divisional domains.   
   
   
       13 . The memory device according to  claim 12 , wherein multiple memory cells associated with one divisional word line in each of the divisional domains store an integral number of either vertical or horizontal arrays of pixel data constituting an image data. 
   
   
       14 . A motion vector detector for detecting a motion vector from a reference frame and a search frame that are displaced in time, comprising: a first memory unit for storing multiple items of pixel data constituting said reference frame;
 a second memory unit for receiving pixel data of the reference block read out of said first memory unit as reference data and for calculating differences between the pixel data in multiple candidate blocks in the search area associated with said reference block and the pixel data of said reference block every corresponding item of pixel data, in relation to the respective multiple candidate blocks; and   a motion vector detection unit for detecting a motion vector associated with said reference block, based on said differences for each of the items of pixel data in relation to the respective multiple candidate blocks operated in said second memory unit,   wherein said first memory unit comprises one or more first semiconductor memory blocks, and said second memory unit comprises one or more second semiconductor memory blocks;   wherein said first semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines; and   multiple memory cells arranged in a matrix form and connected to said bit lines and said word lines,   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line;   wherein each of said multiple selection lines has multiple divisional word lines divided corresponding to said multiple divisional domains;   wherein said first semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in the divisional domains;   wherein said second semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines;   a reference data input line for receiving reference data, said reference data input lines perpendicularly crossing said bit lines or parallel extending along said bit lines;   an operation data output line for outputting operation data, said operation data output lines perpendicularly crossing said multiple said bit lines or parallel extending along said bit lines;   a cell selection line for receiving cell selection signal, said cell selection line perpendicularly crossing said multiple word lines or parallel extending along said multiple word lines;   multiple memory cells arranged in a matrix form, said cells being connected with said bit lines, said word lines, said reference data input line, said operation data output line, and said cell selection line; and,   an ancillary operational cell for performing a numerical calculation using at least a part of said operation data outputted from said multiple operation data output line to obtain said differences,   wherein said memory cell includes:   a memory cell unit for storing data of “1” or “0”;   a reference data input unit for receiving said reference data, said reference data input unit being connected with said reference data input line;   an operation function unit for executing an logical operation using the memory data stored in said memory cell unit and reference data received from said reference data input unit;   an operation data output unit for outputting the operation data obtained in said operation function unit to said operation data output line, said operation data output unit being connected with said operation data output line;   a cell selection signal input unit for receiving said cell selection signal, said cell selection signal input unit being connected with said cell selection line; and   an output control unit for outputting to said operation data output unit said operation data obtained by the operation in said operation function unit, based on said cell selection signal received in said cell selection signal input unit,   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the cell selection line;   wherein each of said multiple selection lines has said multiple divisional cell selection lines divided corresponding to the multiple divisional domains; and   wherein said second semiconductor memory block further has switching mechanism for switching the divisional cell selection lines that are simultaneously activated in the associated divisional domain.   
   
   
       15 . The motion vector detector according to  claim 14 , wherein multiple memory cells associated with one divisional cell selection line in each of the divisional domains store an integral number of either vertical or horizontal arrays of pixel data constituting an image data. 
   
   
       16 . A motion compensation prediction encoder for detecting a motion vector in a motion vector detection circuit from a reference frame and a search frame that are displaced in time, and performing motion compensation using the motion vector, wherein said motion vector detection circuit comprises:
 a first memory unit for storing multiple items of pixel data constituting said reference frame;   a second memory unit for storing multiple items of pixel data constituting said search frame;   an operation unit for receiving pixel data of the reference block read out of said first memory unit and pixel data of multiple candidate blocks in the search block, said pixel data of multiple candidate blocks being associated with said reference block and read out of said second memory unit, and for calculating differences between the pixel data in said multiple candidate blocks and the pixel data of said reference block every corresponding item of pixel data, in relation to the respective multiple candidate blocks; and   a motion vector detection unit for detecting a motion vector associated with said reference block based on said differences calculated for each of the items of pixel data in relation to the respective multiple candidate blocks operated in said operation unit,   wherein each of said first and second memory units comprises one or more semiconductor memory block, respectively;   wherein said semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines; and   multiple memory cells arranged in a matrix form and connected with said bit lines and said word lines;   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line;   wherein each of said multiple selection lines has multiple divisional word lines divided corresponding to said multiple divisional domains; and   wherein said semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in the associated divisional domain.   
   
   
       17 . A motion compensation prediction encoder for detecting a motion vector in a motion vector detection circuit from a reference frame and a search frame that are displaced in time, and performing motion compensation using the motion vector, wherein said motion vector detection circuit comprises:
 a first memory unit for storing multiple items of pixel data constituting said reference frame;   a second memory unit for receiving pixel data of the reference block read out of said first memory unit as reference data and for calculating differences between the pixel data in multiple candidate blocks in the search area associated with said reference block and the pixel data of said reference block every corresponding item of pixel data of each of the candidate blocks, in relation to the respective multiple candidate blocks; and   a motion vector detection unit for detecting a motion vector associated with said reference block, based on said differences calculated for each of the items of pixel data in relation to the respective multiple candidate blocks operated in said second memory unit,   wherein said first memory unit comprises one or more first semiconductor memory block, and said second memory unit comprises one or more second semiconductor memory block;   wherein said first semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines; and   multiple memory cells arranged in a matrix form and connected to said bit lines and said word lines,   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the word line;   wherein each of said multiple selection lines has multiple divisional word lines divided corresponding to said multiple divisional domains;   wherein said semiconductor memory block further has switching mechanism for switching the divisional word lines that are simultaneously activated in the associated divisional domain;   wherein said second semiconductor memory block has:   multiple bit lines;   multiple word lines perpendicularly crossing said multiple bit lines;   a reference data input line for receiving reference data, said reference data input lines perpendicularly crossing said bit lines or parallel extending along said bit lines;   an operation data output line for outputting operation data, said operation data output lines perpendicularly crossing said multiple bit lines or parallel extending along said bit lines;   a cell selection line for receiving cell selection signal, said cell selection line perpendicularly crossing said multiple word lines or parallel extending along the word lines;   multiple memory cells arranged in a matrix form, said cells being connected with said bit lines, said word lines, said reference data input line, said operation data output line, and said cell selection line; and   an ancillary operational cell for performing numerical calculations using at least a part of said operation data outputted from said multiple operation data output lines to obtain said differences,   wherein said memory cell includes:   a memory cell unit for storing data of “1” or “0”;   a reference data input unit for receiving said reference data, said reference data input unit being connected with said reference data input line;   an operation function unit for executing an logical operation using the memory data stored in said memory cell unit and reference data received from said reference data input unit;   an operation data output unit for outputting the operation data obtained in said operation function unit to said operation data output line, said operation data output unit being connected with said operation data output line;   a cell selection signal input unit for receiving said cell selection signal, said cell selection signal input unit being connected with said cell selection line; and   an output control unit for outputting to said operation data output unit said operation data obtained by the operation in said operation function unit, based on said cell selection signal received in said cell selection signal input unit,   wherein an area of said multiple memory cells arranged in the matrix form has multiple divisional domains divided in a direction along the cell selection line;   wherein each of said multiple selection lines has said multiple divisional cell selection lines divided according to the multiple divisional domains; and   wherein said second semiconductor memory block further has switching mechanism for switching the divisional cell selection lines that are simultaneously activated in each of the divisional domains.   
   
   
       18 . A memory cell circuit, comprising;
 a memory cell unit for storing data of “1” or “0”; and   multiple access transistors each for connecting said memory cell unit to bit line, said transistors being connected in parallel with each other.   
   
   
       19 . A memory device, comprising:
 first memory cell and second memory cells, said first and second memory cells being arranged in a matrix form and admixed,   wherein said first memory cell is connected with a first word line and a second word line, respectively, and said second memory cell is connected with only said first word line; and   wherein said first word line extends in the column direction of said matrix, while said second word line is provided in an echelon form extending over multiple rows of said matrix.   
   
   
       20 . The memory device according to  claim 19 , wherein said echelon form of said second word line is repeated in the column direction of said matrix by the unit of a predetermined number of memory cells. 
   
   
       21 . The memory device according to  claim 19 , including multiple shared second word lines having different echelon forms. 
   
   
       22 . The memory device according to  claim 21 , wherein said first memory cells connected to said multiple second word lines are different memory cells. 
   
   
       23 . A motion vector detector comprising:
 an image hierarchizing means for producing multiple hierarchical classes of image data having different resolution from input image data;   motion vector detection means for detecting a motion vector of a predetermined position of said input image using block-matching processing, based on said multiple hierarchical classes of image data formed by said image hierarchizing means; and   memory unit for storing said multiple hierarchical classes of image data,   wherein said memory unit has a first memory cell and second a memory cell arranged in a matrix form, said first and second memory cells being arranged in a matrix form and admixed;   wherein said first memory cell is connected with a first word line and a second word line, respectively, and said second memory cell is connected with only said first word line;   wherein said first word line extends in the column direction of said matrix, while said second word line is provided in an echelon form extending over multiple rows of said matrix;   wherein the lowest hierarchical class of said image data among the multiple classes of image data is stored in said second memory cell, and the hierarchical classes of said image data other than the lowest class are stored in said first memory cell.   
   
   
       24 . The motion vector detector according to  claim 23 , including multiple shared second word lines having different echelon forms;
 wherein said first memory cells connected to said multiple second word lines are different memory cells; and   wherein each of the first memory cells connected to said multiple second word lines stores image data belonging to the different hierarchical classes.