Method and leadframe for packaging integrated circuits

Abstract

A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.

1 . An integrated circuit package, comprising:
 a first die, the first die having an active surface and a back surface substantially opposite the active surface of the first die, the active surface including a first plurality of I/O pads;   a second die, the second die having an active surface and a back surface substantially opposite the active surface of the second die, the active surface including a second plurality of I/O pads;   a plurality of leads, each lead having a first side and a second side substantially opposite the first side of the lead, the active surface of the first die being positioned adjacent first sides of selected leads such that I/O pads from the first plurality of I/O pads are arranged adjacent corresponding solder pads on the first sides of the selected leads, the active surface of the second die being positioned adjacent second sides of the selected leads such that I/O pads from the second plurality of I/O pads are arranged adjacent corresponding solder pads on the second sides of the selected leads, each selected lead including at least two solder pads on each of the first and second sides of the lead, each solder pad on a selected lead being isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad; and   a plurality of solder joints that are arranged to physically and electrically connect selected ones of the I/O pads from the first die to corresponding solder pads on the first sides of associated selected leads and to physically and electrically connect selected ones of the I/O pads from the second die to corresponding solder pads on the second sides of the associated selected leads, wherein the solder of each solder joint that contacts an associated solder pad surface on a selected lead is substantially confined to the solder pad surface by one or more adjacent recessed regions.   
   
   
       2 . An integrated circuit package as recited in  claim 1 , wherein each selected lead includes at least three solder pads on each of the first and second sides of the lead. 
   
   
       3 . An integrated circuit package as recited in  claim 1 , wherein the solder pads on the first sides of the selected leads do not directly overlie the solder pads on the second sides of the selected leads. 
   
   
       4 . An integrated circuit package as recited in  claim 1 , wherein the pitch between a solder pad on the first side of a selected lead and a solder pad on the second side of the lead is substantially half the pitch between adjacent solder pads on the same side of the lead. 
   
   
       5 . An integrated circuit package as recited in  claim 1 , wherein the solder pads on the first sides of the selected leads directly overlie the solder pads on the second sides of the selected leads. 
   
   
       6 . A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package, the leadframe comprising:
 a plurality of leads, each of a first set of the plurality of leads having a first side and a second side substantially opposite the first side of the lead, each of the first and second sides of the first set of leads each including at least two solder pads, each solder pad on a lead of the first set of leads being isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad.   
   
   
       7 . A leadframe as recited in  claim 6 , wherein each lead of the first set of leads includes at least three solder pads on each of the first and second sides of the lead. 
   
   
       8 . A leadframe as recited in  claim 6 , wherein each lead of the first set of leads includes at least eight solder pads on each of the first and second sides of the lead. 
   
   
       9 . A leadframe as recited in  claim 6 , wherein the solder pads on the first sides of the first set of leads do not directly overlie the solder pads on the second sides of the leads. 
   
   
       10 . A leadframe as recited in  claim 6 , wherein the pitch between a solder pad on the first side of a lead of the first set of leads and a solder pad on the second side of the lead is substantially half the pitch between adjacent solder pads on the same side of the lead. 
   
   
       11 . A leadframe as recited in  claim 6 , wherein the solder pads on the first sides of the leads of the first set of leads directly overlie the solder pads on the second sides of the leads. 
   
   
       12 . A leadframe as recited in  claim 6 , wherein widths of selected solder pads are wider than their associated leads. 
   
   
       13 . A leadframe as recited in  claim 6 , wherein each recessed region is recessed to a depth in the range of approximately 2 to 4 mils from the surface of the associated solder pad. 
   
   
       14 . A leadframe as recited in  claim 6 , wherein each recessed region is recessed to a depth of approximately half the thickness of the associated lead. 
   
   
       15 . A leadframe as recited in  claim 6 , wherein the solder pads are substantially circular. 
   
   
       16 . A method of packaging at least two integrated circuit dice into a single integrated circuit package utilizing a single leadframe, the method comprising:
 positioning a first die onto a first side of a leadframe such that I/O pads on the first die are positioned adjacent corresponding solder pads on first sides of selected leads of the leadframe;   reflowing solder bumps positioned between the I/O pads on the first die and the solder pads on the first sides of the leads to produce a first plurality of solder joints that physically and electrically connect the first die to the leads of the leadframe;   positioning the leadframe onto a set of spacers such that the first die is below the leadframe, the spacers being arranged to support the leadframe such that the die does not have to contact any other surface;   positioning a second die onto a second side of the leadframe opposite the first side of the leadframe such that I/O pads on the second die are positioned adjacent corresponding solder pads on second sides of the selected leads of the leadframe; and   reflowing solder bumps positioned between the I/O pads on the second die and the solder pads on the second sides of the leads to produce a second plurality of solder joints that physically and electrically connect the second die to the leads of the leadframe, whereby the spacers support the leadframe such that during the second reflowing the first plurality of solder joints are not compressed by the weight of the leadframe.   
   
   
       17 . A method as recited in  claim 16 , wherein the first plurality of solder joints are melted during the second reflowing and wherein the cohesion of the solder is sufficient to support the weight of the first die. 
   
   
       18 . A method as recited in  claim 16 , wherein selected I/O pads on the first die and selected I/O pads from the second die are connected to the same leads. 
   
   
       19 . A method as recited in  claim 16 , wherein multiple I/O pads on the first die are connected with a single selected lead and wherein multiple I/O pads on the second die are connected with the same single selected lead. 
   
   
       20 . A method as recited in  claim 16 , wherein either or both of the first and second sides of the leadframe have I/O pads from at least two dice connected with solder pads on the same side of the leadframe. 
   
   
       21 . A method as recited in  claim 16 , wherein the leadframe is a single leadframe device area of a larger leadframe panel that includes a plurality of device areas each of which is configured for use it packaging at least one die on either side of the leadframe device area. 
   
   
       22 . A method as recited in  claim 21 , further comprising encapsulating the leadframe panel and singulating the leadframe panel to produce a plurality of integrated circuit packages each including at least two dice.