Wafer-level stack package

Abstract

A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.

1 . A wafer-level stack package comprising:
 semiconductor chips stacked on one another, each of the semiconductor chips having a power/ground pad and a signal pad;   first connection members electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips; and   a second connection member electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members.   
   
   
       2 . The wafer-level stack package of  claim 1 , wherein the first connection members are conductive plugs that respectively penetrate regions of the semiconductor chips where the power/ground pad and the signal pad are formed. 
   
   
       3 . The wafer-level stack package of  claim 2 , wherein the second connection member comprises:
 at least one conductive pillar penetrating the semiconductor chips except in a region where the power/ground pad and the signal pad are formed; and   a rewiring provided in at least one of the semiconductor chips, the rewiring connecting the conductive pillar to the power/ground pad of each of the semiconductor chips.   
   
   
       4 . The wafer-level stack package of  claim 3 , wherein the conductive pillar is formed in a scribe lane region of the semiconductor chips to be cut. 
   
   
       5 . The wafer-level stack package of  claim 1 , further comprising:
 a substrate supporting the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member.   
   
   
       6 . The wafer-level stack package of  claim 5 , wherein the first connection members and the second connection member connected to the same power/ground pad are connected to the same wiring of the substrate. 
   
   
       7 . The wafer-level stack package of  claim 5 , further comprising:
 external connection terminals provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.   
   
   
       8 . The wafer-level stack package of  claim 7 , wherein the external connection terminals comprise a solder ball, a metal pin and a metal land. 
   
   
       9 .- 15 . (canceled) 
   
   
       16 . A wafer-level stack package comprising:
 a plurality of stacked semiconductor chips each including a power/ground pad and a signal pad; and   a plurality of connections members electrically connected to each of the power/ground pads and at least one connection member electrically connected to the signal pad of each of the semiconductor chips.   
   
   
       17 . The wafer-level stack package of  claim 16 , wherein first and second groups of the plurality of connection members provide separate connections, respectively, between the power/ground pads to external wirings of the wafer-level package. 
   
   
       18 . The wafer-level stack package of  claim 17 , wherein the first and second groups of the plurality of connection members connected to the same power/ground pads are connected to the same external wirings. 
   
   
       19 . (canceled)