Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines

Abstract

A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements.

1 . A method for testing a delay line forming part of integrated circuit, the method comprising;
 selecting a number n of delay elements in a delay line;   applying a preselected number of calibration pulses having a predetermined time period to the delay line;   for the calibration pulses exiting the delay line, determining logic states a predetermined time period apart for the calibration pulses;   adding at least one delay element; when the determination of the two logic states is not the expected value for the calibration pulses, analyzing the data to determine the delay of each delay element.   
   
   
       2 . The method as recited in  claim 1  further comprising fabricating all components needed to test the delay on the same substrate as the delay line. 
   
   
       3 . Delay line calibration apparatus, the apparatus comprising:
 a selection unit, the selection unit selecting a one of the delay elements in a delay line;   a coupling element, the coupling element coupling the selected one delay element to a beginning of the delay line, the coupling element and the delay line elements providing a ring oscillator;   a counting unit, the counting unit determining the number of oscillations in a ring oscillator; and   a comparison unit, the comparison unit comparing the number of oscillations with a preselected time period.   
   
   
       4 . The apparatus as recited in  claim 3  wherein the apparatus is fabricated on the same substrate as the delay line. 
   
   
       5 . The apparatus as recited in  claim 3  wherein the preselected time period is determined by the system clock. 
   
   
       6 . The apparatus as recited in  claim 3  wherein the calibration of the delay line is performed by components fabricated on the same substrate. 
   
   
       7 . A method for calibrating delay elements in a delay line, the method comprising:
 forming a ring oscillator with selected elements of the delay line; and   determining the number of oscillations of the ring oscillator in a predetermined time period.   
   
   
       8 . The method as recited in  claim 7  further comprising determining the predetermined period of time by the system clock. 
   
   
       9 . The method as recited in  claim 7  further comprising performing the calibration with component fabricated on the same chip as the delay line. 
   
   
       10 . The method as recited in  claim 7  further comprising calibrating the delay line with components fabricated on the same substrate.